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MC100E142 PDF预览

MC100E142

更新时间: 2024-11-18 22:30:23
品牌 Logo 应用领域
安森美 - ONSEMI 移位寄存器
页数 文件大小 规格书
4页 112K
描述
9-BIT SHIFT REGISTER

MC100E142 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10E/100E142 is a 9-bit shift register, designed with byte-parity  
applications in mind. The E142 performs serial/parallel in and  
serial/parallel out, shifting in one direction. The nine inputs D0 – D8  
accept parallel input data, while S-IN accepts serial input data. The Qn  
outputs do not need to be terminated for the shift operation to function. To  
minimize noise and power, any Q output not used should be left  
unterminated.  
9-BIT SHIFT  
REGISTER  
700MHz Min. Shift Frequency  
9-Bit for Byte-Parity Applications  
Asynchronous Master Reset  
Dual Clocks  
Extended 100E V  
Range of – 4.2V to – 5.46V  
EE  
75kInput Pulldown Resistors  
The SEL (Select) input pin is used to switch between the two modes of  
operation — SHIFT and LOAD. The shift direction is from bit 0 to bit 8.  
Input data is accepted by the registers a set-up time before the positive  
going edge of CLK1 or CLK2; shifting is also accomplished on the positive  
clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets  
all the resisters to zero.  
FN SUFFIX  
PLASTIC PACKAGE  
CASE 776-02  
SEL  
25  
D
D
D
D
V
Q
8
8
7
6
5
CCO  
24  
23  
22  
21  
20  
19  
MR  
CLK1  
CLK2  
18  
17  
16  
15  
14  
13  
26  
Q
Q
7
27  
28  
6
LOGIC DIAGRAM  
S-IN  
V
CC  
1
0
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
3
D
D
0
Pinout: 28-Lead PLCC  
V
1
2
EE  
Q
V
5
(Top View)  
S-IN  
1
0
CCO  
D
D
D
D
1
2
D
0
3
Q
4
3
D
1
1
0
4
12  
Q
D
5
6
7
8
9
10  
11  
1
0
D
2
D
D
V
Q
0
Q
1
Q
2
3
4
CCO  
D
3
* All V  
and V  
CCO  
pins are tied together on the die.  
CC  
PIN NAMES  
Pin  
Function  
D
S-IN  
SEL  
CLK1, CLK2  
MR  
– D  
Parallel Data Inputs  
Serial Data Input  
Mode Select Input  
Clock Inputs  
0
8
Q
Q
1
0
8
D
D
8
Master Reset  
SEL  
Q
– Q  
Data Outputs  
0
8
CLK1  
CLK2  
FUNCTIONS  
SEL  
Mode  
MR  
L
H
Load  
Shift  
12/93  
REV 2  
Motorola, Inc. 1996  

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