5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 计数器> MC100E137FNG
MC100E137FNG PDF预览

MC100E137FNG

更新时间： 2024-02-01 09:36:40
品牌 Logo 应用领域
安森美 - ONSEMI 计数器
页数 文件大小 规格书
9页 139K
描述
5 V ECL 8-Bit Ripple Counter

阅读下载

中文翻译

获取价格

MC100E137FNG 数据手册

 浏览型号MC100E137FNG的Datasheet PDF文件第2页浏览型号MC100E137FNG的Datasheet PDF文件第3页浏览型号MC100E137FNG的Datasheet PDF文件第4页浏览型号MC100E137FNG的Datasheet PDF文件第5页浏览型号MC100E137FNG的Datasheet PDF文件第6页浏览型号MC100E137FNG的Datasheet PDF文件第7页 
MC10E137, MC100E137  
5 VꢀECL 8-Bit Ripple Counter  
Description  
The MC10E/100E137 is a very high speed binary ripple counter. The  
two least significant bits were designed with very fast edge rates while  
the more significant bits maintain standard ECLinPS™ output edge  
rates. This allows the counter to operate at very high frequencies while  
maintaining a moderate power dissipation level.  
http://onsemi.com  
The device is ideally suited for multiple frequency clock generation  
as well as a counter in a high performance ATE time measurement  
board.  
Both asynchronous and synchronous enables are available to  
maximize the device’s flexibility for various applications. The  
asynchronous enable input, A_Start, when asserted enables the counter  
while overriding any synchronous enable signals. The E137 features  
XORed enable inputs, EN1 and EN2, which are synchronous to the  
CLK input. When only one synchronous enable is asserted the counter  
becomes disabled on the next CLK transition; all outputs remain in the  
previous state poised for the other synchronous enable or A_Start to be  
asserted to re-enable the counter. Asserting both synchronous enables  
causes the counter to become enabled on the next transition of the CLK.  
If EN1 (or EN2) and CLK edges are coincident, sufficient delay has  
been inserted in the CLK path (to compensate for the XOR gate delay  
and the internal D-flip flop setup time) to insure that the synchronous  
enable signal is clocked correctly, hence, the counter is disabled.  
All input pins left open will be pulled LOW via an input pulldown  
resistor. Therefore, do not leave the differential CLK inputs open.  
Doing so causes the current source transistor of the input clock gate to  
become saturated, thus upsetting the internal bias regulators and  
jeopardizing the stability of the device.  
PLCC−28  
FN SUFFIX  
CASE 776  
MARKING DIAGRAM*  
1
MCxxxE137FNG  
AWLYYWW  
xxx  
A
WL  
YY  
WW  
G
= 10 or 100  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
The asynchronous Master Reset resets the counter to an all zero state  
upon assertion.  
The V pin, an internally generated voltage supply, is available to  
BB  
*For additional marking information, refer to  
Application Note AND8002/D.  
this device only. For single-ended input conditions, the unused  
differential input is connected to V as a switching reference voltage.  
BB  
V
V
may also rebias AC coupled inputs. When used, decouple V and  
via a 0.01 mF capacitor and limit current sourcing or sinking to  
BB  
BB  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
CC  
0.5 mA. When not used, V should be left open.  
BB  
The 100 Series contains temperature compensation.  
Features  
• Differential Clock Input and Data Output Pins  
• ESD Protection: Human Body Model: > 2 kV,  
Machine Model: > 200 V  
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC  
Latchup Test  
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3  
For Additional Information, see Application Note  
AND8003/D  
• Flammability Rating: UL 94 V−0 @ 0.125 in,  
Oxygen Index: 28 to 34  
• V Output for Single-Ended Use  
BB  
• Synchronous and Asynchronous Enable Pins  
• Asynchronous Master Reset  
• PECL Mode Operating Range: V = 4.2 V to 5.7 V  
CC  
with V = 0 V  
EE  
• NECL Mode Operating Range: V = 0 V  
CC  
with V = −4.2 V to −5.7 V  
EE  
• Internal Input 50 kW Pull−down Resistors  
• Transistor Count = 330 devices  
• Pb−Free Packages are Available*  
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting  
Techniques Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 − Rev. 8  
MC10E137/D  
1234567...9

中文翻译

下载PDF

MC100E137FNG 替代型号

型号 品牌 替代类型 描述 数据表
MC100E137FNR2G ONSEMI

类似代替

 5 V ECL 8-Bit Ripple Counter
MC10E137FNR2G ONSEMI

类似代替

 5 V ECL 8-Bit Ripple Counter

与MC100E137FNG相关器件

型号 品牌 获取价格 描述 数据表
MC100E137FNR2 ONSEMI

获取价格

 		5 V ECL 8-Bit Ripple Counter
MC100E137FNR2G ONSEMI

获取价格

 		5 V ECL 8-Bit Ripple Counter
MC100E141 ONSEMI

获取价格

 		8-BIT SHIFT REGISTER
MC100E141FN MOTOROLA

获取价格

 		8-BIT SHIFT REGISTER
MC100E141FN ONSEMI

获取价格

 		5V ECL 8-Bit Shift Register
MC100E141FNG ONSEMI

获取价格

 		5V ECL 8-Bit Shift Register
MC100E141FNR2 ONSEMI

获取价格

 		5V ECL 8-Bit Shift Register
MC100E141FNR2G ONSEMI

获取价格

 		5V ECL 8-Bit Shift Register
MC100E142 ONSEMI

获取价格

 		9-BIT SHIFT REGISTER
MC100E142FN MOTOROLA

获取价格

 		9-BIT SHIFT REGISTER

与MC100E137FNG相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证