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MC100E151 PDF预览

MC100E151

更新时间: 2024-11-18 22:46:23
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
4页 108K
描述
6-BIT D REGISTER

MC100E151 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave  
flip-flops with differential outputs. Data enters the master when both CLK1  
and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2  
(or both) go HIGH. The asynchronous Master Reset (MR) makes all Q  
outputs go LOW.  
1100MHz Min. Toggle Frequency  
Differential Outputs  
6-BIT D REGISTER  
Asynchronous Master Reset  
Dual Clocks  
Extended 100E V  
EE  
Range of – 4.2V to – 5.46V  
75kInput Pulldown Resistors  
LOGIC DIAGRAM  
Q
Q
D
D
D
D
D
0
0
0
R
R
R
R
R
R
Q
Q
D
D
D
FN SUFFIX  
PLASTIC PACKAGE  
CASE 776-02  
1
1
2
3
1
Q
Q
2
2
Q
Q
3
3
Pinout: 28-Lead PLCC (Top View)  
MR CLK2 CLK1  
NC  
V
Q
Q
CCO  
5
5
D
Q
Q
4
5
D
D
4
25  
24  
23  
22  
21  
20  
19  
D
Q
Q
V
26  
18  
17  
16  
15  
14  
13  
5
4
4
D
27  
28  
4
4
D
Q
Q
D
5
3
CC  
5
V
Q
1
2
EE  
3
3
2
2
D
Q
Q
Q
2
CLK1  
CLK2  
3
D
D
1
0
MR  
4
12  
PIN NAMES  
Pin  
Function  
5
6
7
8
9
10  
11  
D
– D  
Data Inputs  
0
5
NC  
V
Q
Q
Q
Q
V
CCO  
CCO  
0
0
1
1
CLK1, CLK2  
Clock Inputs  
Master Reset  
True Outputs  
Inverted Outputs  
MR  
* All V  
and V  
pins are tied together on the die.  
CC  
CCO  
Q
Q
– Q  
– Q  
0
0
5
5
12/93  
Motorola, Inc. 1996  
REV 2  

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