Datasheet > MC100E154

MC100E154

更新时间： 2024-11-18 22:46:23

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
4页	111K
描述
5-BIT 2:1 MUX-LATCH

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数据手册

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MC100E154 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC10E/100E154 contains five 2:1 multiplexers followed by

transparent latches with differential outputs. When both Latch Enables

(LEN1, LEN2) are LOW, the latch is transparent, and output data is

controlled by the multiplexer select control, SEL. A logic HIGH on either

LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR)

overrides all other controls to set the Q outputs LOW.

5-BIT 2:1

• 850ps Max. LEN to Output

• 825ps Max. D to Output

• Differential Outputs

MUX-LATCH

• Asynchronous Master Reset

• Dual Latch-Enables

• Extended 100E V

Range of – 4.2V to – 5.46V

• 75kΩ Input Pulldown Resistors

Pinout: 28-Lead PLCC (Top View)

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

CCO

SEL

LEN1

LEN2

LOGIC DIAGRAM

MUX

SEL

MUX

SEL

MUX

SEL

CCO

* All V

and V

CCO

pins are tied together on the die.

MUX

SEL

PIN NAMES

Function

SEL

– D

Input Data a

Input Data b

MUX

SEL

Data Select Input

Latch Enables

Master Reset

True Outputs

Inverted Outputs

LEN1, LEN2

– Q

SEL

LEN1

LEN2

TRUTH TABLE

SEL

Data

12/93

REV 2

2–1

Motorola, Inc. 1996

12 3 4

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与MC100E154相关器件

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MC100E154FN	MOTOROLA	获取价格	5-BIT 2:1 MUX-LATCH
MC100E154FN	ONSEMI	获取价格	5V ECL 5-Bit 2:1 Mux-Latch
MC100E154FNR2	ONSEMI	获取价格	5V ECL 5-Bit 2:1 Mux-Latch
MC100E155	ONSEMI	获取价格	6-BIT 2:1 MUX-LATCH
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MC100E155FN	ONSEMI	获取价格	5V ECL 6−Bit 2:1 Mux−Latch
MC100E155FNR2	ONSEMI	获取价格	5V ECL 6−Bit 2:1 Mux−Latch
MC100E156	ONSEMI	获取价格	3-BIT 4:1 MUX-LATCH
MC100E156FN	ONSEMI	获取价格	5V ECL 3-Bit 4:1 Mux-Latch
MC100E156FN	MOTOROLA	获取价格	3-BIT 4:1 MUX-LATCH