Datasheet > MC100E156

MC100E156

更新时间： 2024-11-18 22:46:23

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
4页	110K
描述
3-BIT 4:1 MUX-LATCH

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数据手册

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MC100E156 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC10E/100E156 contains three 4:1 multiplexers followed by

transparent latches with differential outputs. When both Latch Enables

(LEN1, LEN2) are LOW, the latch is transparent, and output date is

controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH

on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset

(MR) overrides all other controls to set the Q outputs LOW.

3-BIT 4:1

MUX-LATCH

• 950ps Max. D to Output

• 850ps Max. LEN to Output

• Differential Outputs

• Asynchronous Master Reset

• Dual Latch-Enables

• Extended 100E V

Range of – 4.2V to – 5.46V

• 75kΩ Input Pulldown Resistors

Pinout: 28-Lead PLCC (Top View)

D b

D a

D d

D c

D b

D a

CCO

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

SEL0

SEL1

LOGIC DIAGRAM

LEN1

LEN2

D a

D b

4:1

MUX

CCO

D c

D d

D a

D d

D a

D b

D c

D d

CCO

D b

4:1

MUX

D c

D d

* All V

and V

pins are tied together on the die.

CCO

PIN NAMES

Function

D a

D b

4:1

MUX

D x – D x

Input Data

D c

SEL0, SEL1

LEN1, LEN2

Select Inputs

Latch Enables

Master Reset

True Outputs

Inverted Outputs

D d

– Q

SEL0

SEL1

LEN1

LEN2

FUNCTION TABLE

SEL1

SEL0

Data

7/96

REV 3

2–1

Motorola, Inc. 1996

12 3 4

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