MC100E155

更新时间： 2024-09-28 22:46:23

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
4页	109K
描述
6-BIT 2:1 MUX-LATCH

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中文翻译

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数据手册

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MC100E155 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC10E/100E155 contains six 2:1 multiplexers followed by

transparent latches with single-ended outputs. When both Latch Enables

(LEN1, LEN2) are LOW, the latch is transparent, and output data is

controlled by the multiplexer select control, SEL. A logic HIGH on either

LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR)

overrides all other controls to set the Q outputs LOW.

6-BIT 2:1

MUX-LATCH

• 850ps Max. LEN to Output

• 825ps Max. D to Output

• Single-Ended Outputs

• Asynchronous Master Reset

• Dual Latch-Enables

• Extended 100E V

Range of – 4.2V to – 5.46V

• 75kΩ Input Pulldown Resistors

Pinout: 28-Lead PLCC (Top View)

D a

D b

D a

D b

D a

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

CCO

D b

LEN1

LEN2

LOGIC DIAGRAM

D a

MUX

SEL

D b

D a

MUX

SEL

D b

CCO

D a

MUX

SEL

D a

D b

D a

D b

CCO

D a

MUX

SEL

* All V

and V

CCO

pins are tied together on the die.

D b

D a

PIN NAMES

MUX

SEL

Function

D b

D a – D

Input Data a

Input Data b

Data Select Input

Latch Enables

Master Reset

Outputs

SEL

D a

D b – D b

MUX

SEL

LEN1, LEN2

D b

– Q

SEL

TRUTH TABLE

SEL

LEN1

LEN2

Data

5/95

REV 3

2–1

Motorola, Inc. 1996

12 3 4

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