5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 时钟驱动器> MC100E111FNG
MC100E111FNG PDF预览

MC100E111FNG

更新时间： 2024-11-19 05:10:27
品牌 Logo 应用领域
安森美 - ONSEMI 时钟驱动器
页数 文件大小 规格书
10页 144K
描述
5V ECL 1:9 Differential Clock Driver

阅读下载

中文翻译

获取价格

MC100E111FNG 技术参数

是否无铅： 不含铅生命周期：Active
零件包装代码：QLCC包装说明：QCCJ, LDCC28,.5SQ
针数：28Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：1.04
其他特性：NECL MODE: VCC = 0 V WITH VEE = -4.2 V TO -5.7 V系列：100E
输入调节：DIFFERENTIALJESD-30 代码：S-PQCC-J28
JESD-609代码：e3长度：11.505 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER湿度敏感等级：3
功能数量：1反相输出次数：
端子数量：28实输出次数：9
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC28,.5SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：260电源：-4.5 V
Prop。Delay @ Nom-Sup：0.66 ns传播延迟（tpd）：0.78 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.075 ns
座面最大高度：4.57 mm子类别：Clock Drivers
最大供电电压 (Vsup)：5.7 V最小供电电压 (Vsup)：4.2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：ECL温度等级：INDUSTRIAL
端子面层：Tin (Sn)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：11.505 mm
Base Number Matches：1

MC100E111FNG 数据手册

 浏览型号MC100E111FNG的Datasheet PDF文件第2页浏览型号MC100E111FNG的Datasheet PDF文件第3页浏览型号MC100E111FNG的Datasheet PDF文件第4页浏览型号MC100E111FNG的Datasheet PDF文件第5页浏览型号MC100E111FNG的Datasheet PDF文件第6页浏览型号MC100E111FNG的Datasheet PDF文件第7页 
MC10E111, MC100E111  
5VꢀECL 1:9 Differential  
Clock Driver  
Description  
The MC10E/100E111 is a low skew 1-to-9 differential driver,  
designed with clock distribution in mind. It accepts one signal input,  
http://onsemi.com  
which can be either differential or else single-ended if the V output  
BB  
is used. The signal is fanned out to 9 identical differential outputs. An  
enable input is also provided. A HIGH disables the device by forcing  
all Q outputs LOW and all Q outputs HIGH.  
The device is specifically designed, modeled and produced with low  
skew as the key goal. Optimal design and layout serve to minimize  
gate to gate skew within-device, and empirical modeling is used to  
PLCC−28  
FN SUFFIX  
CASE 776  
determine process control limits that ensure consistent t  
pd  
distributions from lot to lot. The net result is a dependable, guaranteed  
low skew device.  
MARKING DIAGRAM*  
The lowest TPD delay time results from terminating only one output  
pair, and the greatest TPD delay time results from terminating all the  
output pairs. This shift is about 10 – 20 pS in TPD. The skew between  
any two output pairs within a device is typically about 25 nS. If other  
output pairs are not terminated, the lowest TPD delay time results  
from both output pairs and the skew is typically 25 nS. When all  
outputs are terminated, the greatest TPD (delay time) occurs and all  
outputs display about the same 10 – 20 pS increase in TPD, so the  
relative skew between any two output pairs remains about 25 nS.  
1
MCxxxE111G  
AWLYYWW  
xxx  
A
WL  
YY  
WW  
G
= 10 or 100  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
The V pin, an internally generated voltage supply, is available to  
BB  
this device only. For single-ended input conditions, the unused  
differential input is connected to V as a switching reference voltage.  
BB  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
*For additional marking information, refer to  
Application Note AND8002/D.  
to 0.5 mA. When not used, V should be left open.  
BB  
The 100 Series contains temperature compensation.  
Features  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
• Guaranteed Skew Spec  
• Differential Design  
• V Output  
BB  
• PECL Mode Operating Range: V = 4.2 V to 5.7 V  
• Moisture Sensitivity Level:  
CC  
with V = 0 V  
Pb = 1  
EE  
Pb−Free = 3  
• NECL Mode Operating Range: V = 0 V  
CC  
For Additional Information, see Application Note  
AND8003/D  
• Flammability Rating: UL 94 V−0 @ 0.125 in,  
Oxygen Index: 28 to 34  
• Transistor Count = 178 devices  
• Pb−Free Packages are Available*  
with V = −4.2 V to −5.7 V  
EE  
• Internal Input 50 KW Pulldown Resistors  
• ESD Protection: Human Body Model; > 3 kV  
• Meets or Exceeds JEDEC Standard EIA/JESD78 IC  
Latchup Test  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 − Rev. 16  
MC10E111/D  
1234567...10

中文翻译

下载PDF

MC100E111FNG 替代型号

型号 品牌 替代类型 描述 数据表
MC100E111FNR2G ONSEMI

完全替代

 5V ECL 1:9 Differential Clock Driver
MC100LVE111FNR2G ONSEMI

类似代替

 3.3V ECL 1:9 Differential Clock Driver
MC100LVE111FNG ONSEMI

类似代替

 3.3V ECL 1:9 Differential Clock Driver

与MC100E111FNG相关器件

型号 品牌 获取价格 描述 数据表
MC100E111FNR2 ONSEMI

获取价格

 		5V ECL 1:9 Differential Clock Driver
MC100E111FNR2G ONSEMI

获取价格

 		5V ECL 1:9 Differential Clock Driver
MC100E112 ONSEMI

获取价格

 		QUAD DRIVER
MC100E112FN MOTOROLA

获取价格

 		QUAD DRIVER
MC100E112FN ONSEMI

获取价格

 		5V ECL Quad Driver
MC100E112FNG ONSEMI

获取价格

 		5V ECL Quad Driver
MC100E112FNR2 ONSEMI

获取价格

 		5V ECL Quad Driver
MC100E112FNR2 MOTOROLA

获取价格

 		Inverter/Buffer, 100E Series, 4-Func, 1-Input, ECL, PQCC28, PLASTIC, LCC-28
MC100E112FNR2G ONSEMI

获取价格

 		5V ECL Quad Driver
MC100E116 ONSEMI

获取价格

 		5V ECL Quint Differential Line Receiver

与MC100E111FNG相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证