MC100E131

更新时间： 2024-02-11 17:32:23

品牌	Logo	应用领域
安森美 - ONSEMI		触发器
页数	文件大小	规格书
4页	108K
描述
4-BIT D FLIP-FLOP

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数据手册

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MC100E131 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC10E/100E131 is a quad master-slave D-type flip-flop with

differential outputs. Each flip-flop may be clocked separately by holding

Common Clock (C ) LOW and using the Clock Enable (CE) inputs for

clocking. Common clocking is achieved by holding the CE inputs LOW

and using C to clock all four flip-flops. In this case, the CE inputs perform

the function of controlling the common clock, to each flip-flop.

4-BIT

D FLIP-FLOP

Individual asynchronous resets are provided (R). Asynchronous set

controls (S) are ganged together in pairs, with the pairing chosen to

reflect physical chip symmetry.

Data enters the master when both C and CE are LOW, and transfers

to the slave when either C or CE (or both) go HIGH.

• 1100MHz Min. Toggle Frequency

• Differential Outputs

• Individual and Common Clocks

• Individual Resets (asynchronous)

• Paired Sets (asynchronous)

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

• Extended 100E V

Range of – 4.2V to – 5.46V

• 75kΩ Input Pulldown Resistors

Pinout: 28-Lead PLCC (Top View)

CCO

LOGIC DIAGRAM

CCO

* All V

and V

CCO

pins are tied together on the die.

PIN NAMES

Function

– D

Data Inputs

Clock Enables (Individual)

Resets

CE – CE

– R

Common Clock

Sets (paired)

, S

03 12

– Q

True Outputs

– Q

Inverting Outputs

7/96

Motorola, Inc. 1996

REV 3

2–1

12 3 4

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