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MC100LVE111FNG PDF预览

MC100LVE111FNG

更新时间： 2024-11-19 04:59:43
品牌 Logo 应用领域
安森美 - ONSEMI 时钟驱动器
页数 文件大小 规格书
8页 130K
描述
3.3V ECL 1:9 Differential Clock Driver

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中文翻译

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MC100LVE111FNG 技术参数

是否无铅： 不含铅生命周期：Active
零件包装代码：QLCC包装说明：QCCJ, LDCC28,.5SQ
针数：28Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：1.4
其他特性：NECL MODE: VCC = 0V WITH VEE = -3V TO -3.8V系列：100LVE
输入调节：DIFFERENTIALJESD-30 代码：S-PQCC-J28
JESD-609代码：e3长度：11.505 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER湿度敏感等级：3
功能数量：1反相输出次数：
端子数量：28实输出次数：9
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC28,.5SQ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：260
电源：+-3/+-3.8 VProp。Delay @ Nom-Sup：0.65 ns
传播延迟（tpd）：0.68 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.05 ns座面最大高度：4.57 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.8 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：ECL
温度等级：INDUSTRIAL端子面层：Tin (Sn)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：11.505 mmBase Number Matches：1

MC100LVE111FNG 数据手册

 浏览型号MC100LVE111FNG的Datasheet PDF文件第2页浏览型号MC100LVE111FNG的Datasheet PDF文件第3页浏览型号MC100LVE111FNG的Datasheet PDF文件第4页浏览型号MC100LVE111FNG的Datasheet PDF文件第5页浏览型号MC100LVE111FNG的Datasheet PDF文件第6页浏览型号MC100LVE111FNG的Datasheet PDF文件第7页 
MC100LVE111  
3.3VꢀECL 1:9 Differential  
Clock Driver  
The MC100LVE111 is a low skew 1−to−9 differential driver,  
designed with clock distribution in mind. The MC100LVE111’s  
function and performance are similar to the popular MC100E111, with  
the added feature of low voltage operation. It accepts one signal input,  
http://onsemi.com  
which can be either differential or single−ended if the V output is  
BB  
used. The signal is fanned out to 9 identical differential outputs.  
The LVE111 is specifically designed, modeled and produced with  
low skew as the key goal. Optimal design and layout serve to minimize  
gate to gate skew within a device, and empirical modeling is used to  
MARKING  
DIAGRAM*  
1 28  
determine process control limits that ensure consistent t  
pd  
distributions from lot to lot. The net result is a dependable, guaranteed  
low skew device.  
MC100LVE111G  
AWLYYWW  
To ensure that the tight skew specification is met it is necessary that  
both sides of the differential output are terminated into 50 W, even if  
only one side is being used. In most applications, all nine differential  
pairs will be used and therefore terminated. In the case where fewer  
than nine pairs are used, it is necessary to terminate at least the output  
pairs on the same package side as the pair(s) being used on that side, in  
order to maintain minimum skew. Failure to do this will result in small  
degradations of propagation delay (on the order of 10−20 ps) of the  
output(s) being used which, while not being catastrophic to most  
designs, will mean a loss of skew margin.  
PLCC−28  
FN SUFFIX  
CASE 776  
A
= Assembly Location  
WL  
YY  
WW  
G
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
*For additional marking information, refer to  
Application Note AND8002/D.  
The MC100LVE111, as with most other ECL devices, can be  
operated from a positive V supply in PECL mode. This allows the  
CC  
LVE111 to be used for high performance clock distribution in +3.3 V  
systems. Designers can take advantage of the LVE111’s performance  
to distribute low skew clocks across the backplane or the board. In a  
PECL environment, series or Thevenin line terminations are typically  
used as they require no additional power supplies. For systems  
incorporating GTL, parallel termination offers the lowest power by  
taking advantage of the 1.2 V supply as a terminating voltage. For  
more information on using PECL, designers should refer to  
Application Note AN1406/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
*For additional information on our Pb−Free strategy  
and soldering details, please download the  
ON Semiconductor Soldering and Mounting  
Techniques Reference Manual, SOLDERRM/D.  
The V pin, an internally generated voltage supply, is available to  
BB  
this device only. For single−ended input conditions, the unused  
differential input is connected to V as a switching reference voltage.  
BB  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
to 0.5 mA. When not used, V should be left open.  
BB  
Features  
• 200 ps Part−to−Part Skew  
• 50 ps Output−to−Output Skew  
• The 100 Series Contains Temperature Compensation  
• PECL Mode Operating Range: V = 3.0 V to 3.8 V with V = 0 V  
CC  
EE  
• NECL Mode Operating Range: V = 0 V with V = −3.0 V to −3.8 V  
CC  
EE  
• Internal Input Pulldown Resistors  
• Q Output will Default LOW with Inputs Open or at V  
• Pb−Free Packages are Available*  
EE  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 − Rev. 7  
MC100LVE111/D  
12345678

中文翻译

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MC100LVE111FNG 替代型号

型号 品牌 替代类型 描述 数据表
MC100LVE111FN ONSEMI

完全替代

 LOW-VOLTAGE 1:9 DIFFERENTIAL ECL/PECL CLOCK DRIVER
MC100LVE111FNR2G ONSEMI

类似代替

 3.3V ECL 1:9 Differential Clock Driver

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