Datasheet > MC100LVE310_06

MC100LVE310_06

更新时间： 2024-11-11 03:20:19

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
7页	129K
描述
3.3V ECL 2:8 Differential Fanout Buffer

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MC100LVE310_06 数据手册

MC100LVE310

3.3VꢀECL 2:8 Differential

Fanout Buffer

Description

The MC100LVE310 is a low voltage, low skew 2:8 differential ECL

fanout buffer designed with clock distribution in mind. The device

features fully differential clock paths to minimize both device and

system skew. The LVE310 offers two selectable clock inputs to allow

for redundant or test clocks to be incorporated into the system clock

trees.

http://onsemi.com

To ensure that the tight skew specification is met it is necessary that

both sides of the differential output are terminated into 50 W, even if

only one side is being used. In most applications all eight differential

pairs will be used and therefore terminated. In the case where fewer

than eight pairs are used it is necessary to terminate at least the output

pairs adjacent to the output pair being used in order to maintain

minimum skew. Failure to follow this guideline will result in small

degradations of propagation delay (on the order of 10 − 20 ps) of the

outputs being used, while not catastrophic to most designs this will

result in an increase in skew. Note that the package corners isolate

outputs from one another such that the guideline expressed above

holds only for outputs on the same side of the package.

PLCC−28

FN SUFFIX

CASE 776

MARKING DIAGRAM*

MC100LVE310G

AWLYYWW

The MC100LVE310, as with most ECL devices, can be operated

from a positive V

supply in LVPECL mode. This allows the

LVE310 to be used for high performance clock distribution in +3.3 V

systems. Designers can take advantage of the LVE310’s performance

to distribute low skew clocks across the backplane or the board. In a

PECL environment series or Thevenin line terminations are typically

used as they require no additional power supplies, if parallel

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

termination is desired a terminating voltage of V − 2.0 V will need

to be provided. For more information on using PECL, designers

should refer to Application Note AN1406/D.

*For additional marking information, refer to

Application Note AND8002/D.

The V pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

differential input is connected to V as a switching reference voltage.

may also rebias AC coupled inputs. When used, decouple V

and V via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, V should be left open.

Features

• 200 ps Part−to−Part Skew

• 50 ps Output−to−Output Skew

• PECL Mode Operating Range:

• Q Output will Default LOW with All Inputs Open or

at V

• The 100 Series Contains Temperature Compensation

• Pb−Free Packages are Available*

= 3.0 V to 3.8 V with V = 0 V

• NECL Mode Operating Range:

= 0 V with V = −3.0 V to −3.8 V

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Publication Order Number:

November, 2006 − Rev. 4

MC100LVE310/D

12 3 4 5 6 7

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与MC100LVE310_06相关器件

型号	品牌	获取价格	描述	数据表
MC100LVE310FN	ONSEMI	获取价格	3.3V ECL 2:8 Differential Fanout Buffer
MC100LVE310FN	MOTOROLA	获取价格	LOW VOLTAGE 2:8 DIFFERENTIAL FANOUT BUFFER
MC100LVE310FNG	ONSEMI	获取价格	3.3V ECL 2:8 Differential Fanout Buffer
MC100LVE310FNR2	ONSEMI	获取价格	3.3V ECL 2:8 Differential Fanout Buffer
MC100LVE310FNR2G	ONSEMI	获取价格	3.3V ECL 2:8 Differential Fanout Buffer
MC100LVEL01	ONSEMI	获取价格	4-Input OR/NOR
MC100LVEL01_06	ONSEMI	获取价格	3.3V ECL 4−Input OR/NOR
MC100LVEL01D	ONSEMI	获取价格	3.3V ECL 4−Input OR/NOR
MC100LVEL01D	MOTOROLA	获取价格	4-Input OR/NOR
MC100LVEL01DG	ONSEMI	获取价格	3.3V ECL 4−Input OR/NOR

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