Datasheet > 逻辑 > 时钟驱动器> MC100LVE210FNR2G

MC100LVE210FNR2G

更新时间： 2024-11-11 04:59:43

品牌	Logo	应用领域
安森美 - ONSEMI		时钟驱动器逻辑集成电路
页数	文件大小	规格书
8页	85K
描述
3.3V ECL Dual 1:4, 1:5 Differential Fanout Buffer

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MC100LVE210FNR2G 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QLCC
包装说明：	QCCJ, LDCC28,.5SQ	针数：	28
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
Factory Lead Time：	1 week	风险等级：	5.44
Is Samacsys：	N	其他特性：	NECL MODE: VCC = 0V WITH VEE = -3V TO -3.8V
系列：	100LVE	输入调节：	DIFFERENTIAL
JESD-30 代码：	S-PQCC-J28	JESD-609代码：	e3
长度：	11.505 mm	逻辑集成电路类型：	LOW SKEW CLOCK DRIVER
功能数量：	2	反相输出次数：
端子数量：	28	实输出次数：	4
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC28,.5SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	260
电源：	-3.3 V	Prop。Delay @ Nom-Sup：	0.75 ns
传播延迟（tpd）：	0.9 ns	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.075 ns	座面最大高度：	4.57 mm
子类别：	Clock Drivers	最大供电电压 (Vsup)：	3.8 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	ECL
温度等级：	INDUSTRIAL	端子面层：	Tin (Sn)
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	11.505 mm	Base Number Matches：	1

MC100LVE210FNR2G 数据手册

MC100LVE210

3.3VꢀECL Dual 1:4, 1:5

Differential Fanout Buffer

Description

The MC100LVE210 is a low voltage, low skew dual differential ECL

fanout buffer designed with clock distribution in mind. The device features

two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device

features fully differential clock paths to minimize both device and system

skew. The dual buffer allows for the fanout of two signals through a single

chip, thus reducing the skew between the two fundamental signals from a

part−to−part skew down to an output−to−output skew. This capability

reduces the skew by a factor of 4 as compared to using two LVE111’s to

accomplish the same task.

To ensure that the tight skew specification is met it is necessary that both

sides of the differential output are identically terminated, even if only one

side is being used. In most applications all nine differential pairs will be

used and therefore terminated. In the case where fewer than nine pairs are

used it is necessary to terminate at least the output pairs adjacent to the

output pair being used in order to maintain minimum skew. Failure to

follow this guideline will result in small degradations of propagation delay

(on the order of 10−20 ps) of the outputs being used, while not catastrophic

to most designs this will result in an increase in skew. Note that the

package corners isolate outputs from one another such that the guideline

expressed above holds only for outputs on the same side of the package.

The MC100LVE210, as with most ECL devices, can be operated from a

http://onsemi.com

MARKING

DIAGRAM*

128

MC100LVE210G

AWLYYWW

PLCC−28

FN SUFFIX

CASE 776

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

positive V supply in PECL mode. This allows the LVE210 to be used

*For additional marking information, refer to

Application Note AND8002/D.

for high performance clock distribution in +3.3 V systems. Designers can

take advantage of the LVE210’s performance to distribute low skew clocks

across the backplane or the board. In a PECL environment series or

Thevenin line terminations are typically used as they require no additional

power supplies, if parallel termination is desired a terminating voltage of

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

− 2.0 V will need to be provided. For more information on using

PECL, designers should refer to Application Note AN1406/D.

The V pin, an internally generated voltage supply, is available to this

device only. For single-ended input conditions, the unused differential

input is connected to V as a switching reference voltage. V may also

rebias AC coupled inputs. When used, decouple V and V via a

0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When

not used, V should be left open.

Features

• 200 ps Part−to−Part Skew

• 50 ps Typical Output−to−Output Skew

• The 100 Series Contains Temperature Compensation

• PECL Mode Operating Range: V = 3.0 V to 3.8 V with V = 0 V

• NECL Mode Operating Range: V = 0 V with V = −3.0 V to −3.8 V

• Internal Input Pulldown Resistors

• Q Output will Default LOW with Inputs Open or at V

• Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

December, 2006 − Rev. 7

MC100LVE210/D

12 3 4 5 6 7 8

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与MC100LVE210FNR2G相关器件

型号	品牌	获取价格	描述	数据表
MC100LVE222	ONSEMI	获取价格	Low Voltage 1:15 Differential ±1±2 ECL/PECL C
MC100LVE222_05	ONSEMI	获取价格	3.3 V/5.0 V ECL 1:15 Differential ±1/±2 Clock
MC100LVE222FA	MOTOROLA	获取价格	LOW VOLTAGE 1:15 DIFFERENTIAL ±1/±2 ECL/PECL
MC100LVE222FA	ONSEMI	获取价格	Low Voltage 1:15 Differential ±1±2 ECL/PECL C
MC100LVE222FAG	ONSEMI	获取价格	3.3 V/5.0 V ECL 1:15 Differential ±1/±2 Clock
MC100LVE222FAR2	ONSEMI	获取价格	Low Voltage 1:15 Differential ±1±2 ECL/PECL C
MC100LVE222FAR2G	ONSEMI	获取价格	3.3 V/5.0 V ECL 1:15 Differential ±1/±2 Clock
MC100LVE310	ONSEMI	获取价格	LOW VOLTAGE 2:8 DIFFERENTIAL FANOUT BUFFER
MC100LVE310_06	ONSEMI	获取价格	3.3V ECL 2:8 Differential Fanout Buffer
MC100LVE310FN	ONSEMI	获取价格	3.3V ECL 2:8 Differential Fanout Buffer

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