MC100LVE310

更新时间： 2024-11-10 22:16:11

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
6页	134K
描述
LOW VOLTAGE 2:8 DIFFERENTIAL FANOUT BUFFER

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MC100LVE310 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC100LVE310 is a low voltage, low skew 2:8 differential ECL

fanout buffer designed with clock distribution in mind. The device features

fully differential clock paths to minimize both device and system skew.

The LVE310 offers two selectable clock inputs to allow for redundant or

test clocks to be incorporated into the system clock trees. The

MC100E310 is pin compatible to the National 100310 device. The

MC100LVE310 works from a –3.3V supply while the MC100E310

provides identical function and performance from a standard –4.5V 100E

voltage supply.

LOW VOLTAGE

2:8 DIFFERENTIAL

FANOUT BUFFER

• Dual Differential Fanout Buffers

• 200ps Part–to–Part Skew

• 50ps Output–to–Output Skew

• Low Voltage ECL/PECL Compatible

• 28–lead PLCC Packaging

For applications which require a single–ended input, the V

reference

voltage is supplied. For single–ended input applications the V

reference should be connected to the CLK input and bypassed to ground

FN SUFFIX

PLASTIC PACKAGE

CASE 776–02

via a 0.01µf capacitor. The input signal is then driven into the CLK input.

To ensure that the tight skew specification is met it is necessary that

both sides of the differential output are terminated into 50Ω, even if only

one side is being used. In most applications all nine differential pairs will

be used and therefore terminated. In the case where fewer than nine

pairs are used it is necessary to terminate at least the output pairs

adjacent to the output pair being used in order to maintain minimum skew.

Failure to follow this guideline will result in small degradations of

propagation delay (on the order of 10–20ps) of the outputs being used,

while not catastrophic to most designs this will result in an increase in

skew. Note that the package corners isolate outputs from one another

such that the guideline expressed above holds only for outputs on the

same side of the package.

The MC100LVE310, as with most ECL devices, can be operated from a positive V

supply in PECL mode. This allows the

LVE310 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE310’s

performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line

terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage

of V –2.0V will need to be provided. For more information on using PECL, designers should refer to Motorola Application Note

AN1406/D.

7/95

REV 0.1

4–1

Motorola, Inc. 1996

12 3 4 5 6

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与MC100LVE310相关器件

型号	品牌	获取价格	描述	数据表
MC100LVE310_06	ONSEMI	获取价格	3.3V ECL 2:8 Differential Fanout Buffer
MC100LVE310FN	ONSEMI	获取价格	3.3V ECL 2:8 Differential Fanout Buffer
MC100LVE310FN	MOTOROLA	获取价格	LOW VOLTAGE 2:8 DIFFERENTIAL FANOUT BUFFER
MC100LVE310FNG	ONSEMI	获取价格	3.3V ECL 2:8 Differential Fanout Buffer
MC100LVE310FNR2	ONSEMI	获取价格	3.3V ECL 2:8 Differential Fanout Buffer
MC100LVE310FNR2G	ONSEMI	获取价格	3.3V ECL 2:8 Differential Fanout Buffer
MC100LVEL01	ONSEMI	获取价格	4-Input OR/NOR
MC100LVEL01_06	ONSEMI	获取价格	3.3V ECL 4−Input OR/NOR
MC100LVEL01D	ONSEMI	获取价格	3.3V ECL 4−Input OR/NOR
MC100LVEL01D	MOTOROLA	获取价格	4-Input OR/NOR

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