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M74HCT573TTR PDF预览

M74HCT573TTR

更新时间: 2024-11-22 22:14:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输出元件
页数 文件大小 规格书
11页 231K
描述
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

M74HCT573TTR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:7.2系列:HCT
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:6.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.006 A
湿度敏感等级:3位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:45 ns
传播延迟(tpd):59 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:4.4 mm
Base Number Matches:1

M74HCT573TTR 数据手册

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M74HCT573  
OCTAL D-TYPE LATCH  
WITH 3 STATE OUTPUT NON INVERTING  
HIGH SPEED:  
= 21ns (TYP.) at V = 4.5V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
COMPATIBLE WITH TTL OUTPUTS :  
= 2V (MIN.) V = 0.8V (MAX)  
V
IH  
IL  
DIP  
SOP  
TSSOP  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 6mA (MIN)  
ORDER CODES  
PACKAGE  
OH  
OL  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 573  
TUBE  
T & R  
DIP  
SOP  
M74HCT573B1R  
M74HCT573M1R M74HCT573RM13TR  
M74HCT573TTR  
DESCRIPTION  
The M74HCT573 is an high speed CMOS OCTAL  
LATCH WITH 3-STATE OUTPUTS fabricated  
TSSOP  
2
with silicon gate C MOS technology.  
The 3-State output configuration and the wide  
choice of outline make bus organized system  
simple.  
The M74HCT573 is designed to directly interface  
HSC MOS systems with TTL and NMOS  
This 8-BIT D-Type latches is controlled by a latch  
enable input (LE) and output enable input (OE).  
While the LE input is held at a high level, the Q  
outputs will follow the data input precisely. When  
the LE is taken low, the Q outputs will be latched  
precisely at the logic level of D input data.  
While the OE input is at low level, the eight outputs  
will be in a normal logic state (high or low logic  
level) and while OE is at high level the outputs will  
be in a high impedance state.  
2
components.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/11  

M74HCT573TTR 替代型号

型号 品牌 替代类型 描述 数据表
MC74HCT573ADTR2G ONSEMI

类似代替

Octal 3-State Noninverting Transparent Latch with LSTTL Compatible Inputs
MM74HCT573MTCX FAIRCHILD

功能相似

Bus Driver, HCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 4.40 MM, MO-153AC, TSSOP
SN74HCT573PW TI

功能相似

OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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暂无描述
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