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M74HCT640TTR PDF预览

M74HCT640TTR

更新时间: 2024-11-23 21:05:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
11页 300K
描述
HCT SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDSO20, TSSOP-20

M74HCT640TTR 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84控制类型:COMMON CONTROL
计数方向:BIDIRECTIONAL系列:HCT
JESD-30 代码:R-PDSO-G20长度:6.5 mm
逻辑集成电路类型:BUS TRANSCEIVER最大I(ol):0.006 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
电源:5 VProp。Delay @ Nom-Sup:33 ns
传播延迟(tpd):45 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL翻译:N/A
宽度:4.4 mmBase Number Matches:1

M74HCT640TTR 数据手册

 浏览型号M74HCT640TTR的Datasheet PDF文件第2页浏览型号M74HCT640TTR的Datasheet PDF文件第3页浏览型号M74HCT640TTR的Datasheet PDF文件第4页浏览型号M74HCT640TTR的Datasheet PDF文件第5页浏览型号M74HCT640TTR的Datasheet PDF文件第6页浏览型号M74HCT640TTR的Datasheet PDF文件第7页 
M74HCT640  
OCTAL BUS TRANSCEIVER  
WITH 3 STATE OUTPUTS (INVERTED)  
HIGH SPEED:  
= 13ns (TYP.) at V = 4.5V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
COMPATIBLE WITH TTL OUTPUTS :  
= 2V (MIN.) V = 0.8V (MAX)  
V
IH  
IL  
DIP  
SOP  
TSSOP  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 6mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 640  
TUBE  
T & R  
DIP  
SOP  
M74HCT640B1R  
M74HCT640M1R M74HCT640RM13TR  
M74HCT640TTR  
DESCRIPTION  
The M74HCT640 is an advanced high-speed  
CMOS OCTAL BUS TRANSCEIVER (3-STATE)  
TSSOP  
2
fabricated with silicon gate C MOS technology.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
All floating bus terminals during High Z State must  
be held HIGH or LOW.  
This IC is intended for two-way asynchronous  
communication between data buses, and the  
direction of data transmission is determined by  
DIR input. The enable input G can be used to  
disable the device so that the buses are effectively  
isolated.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/11  

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