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M74HCT640RM13TR PDF预览

M74HCT640RM13TR

更新时间: 2024-11-09 20:03:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
11页 315K
描述
HCT SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDSO20, SOP-20

M74HCT640RM13TR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP20,.4针数:20
Reach Compliance Code:compliantECCN代码:3A001.A.2.C
HTS代码:8542.39.00.01风险等级:8.33
控制类型:COMMON CONTROL计数方向:BIDIRECTIONAL
系列:HCTJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.8 mm
逻辑集成电路类型:BUS TRANSCEIVER最大I(ol):0.006 A
湿度敏感等级:3位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:33 ns
传播延迟(tpd):45 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30翻译:N/A
宽度:7.5 mmBase Number Matches:1

M74HCT640RM13TR 数据手册

 浏览型号M74HCT640RM13TR的Datasheet PDF文件第2页浏览型号M74HCT640RM13TR的Datasheet PDF文件第3页浏览型号M74HCT640RM13TR的Datasheet PDF文件第4页浏览型号M74HCT640RM13TR的Datasheet PDF文件第5页浏览型号M74HCT640RM13TR的Datasheet PDF文件第6页浏览型号M74HCT640RM13TR的Datasheet PDF文件第7页 
M74HCT640  
OCTAL BUS TRANSCEIVER  
WITH 3 STATE OUTPUTS (INVERTED)  
HIGH SPEED:  
= 13ns (TYP.) at V = 4.5V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
COMPATIBLE WITH TTL OUTPUTS :  
= 2V (MIN.) V = 0.8V (MAX)  
V
IH  
IL  
DIP  
SOP  
TSSOP  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 6mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 640  
TBE  
T & R  
DIP  
SOP  
MHCT640B1R  
M74HCT640M1R M74HCT640RM13TR  
M74HCT640TTR  
DESCRIPTION  
The M74HCT640 is an advanced high-speed  
CMOS OCTAL BUS TRANSCEIVER (3-STATE)  
TSSOP  
2
fabricated with silicon gate C MOS technology.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
All floating bus terminals during High Z State must  
be held HIGH or LOW.  
This IC is intended for two-way asynchronous  
communication between data buses, and the  
direction of data transmission is determined by  
DIR input. The enable input G can be used to  
disable the device so that the buses are effectively  
isolated.  
PIN CNNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/11  

M74HCT640RM13TR 替代型号

型号 品牌 替代类型 描述 数据表
CD74HCT640ME4 TI

类似代替

High-Speed CMOS Logic Octal Three-State Bus Transceiver, Inverting
CD74HCT640EE4 TI

类似代替

High-Speed CMOS Logic Octal Three-State Bus Transceiver, Inverting
CD74HCT640MG4 TI

功能相似

High-Speed CMOS Logic Octal Three-State Bus Transceiver, Inverting

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