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M74HCT648B1R PDF预览

M74HCT648B1R

更新时间： 2024-11-22 22:15:35
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
12页 203K
描述
HCT646 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE HCT648 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE, INV.

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M74HCT648B1R 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：DIP
包装说明：PLASTIC, DIP-24针数：24
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.56其他特性：DIRECTION CONTROL; SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED OR REAL TIME DATA
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：HCTJESD-30 代码：R-PDIP-T24
负载电容（CL）：150 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.006 A位数：8
功能数量：1端口数量：2
端子数量：24最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP24,.6
封装形状：RECTANGULAR封装形式：IN-LINE
包装方法：TUBE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 VProp。Delay @ Nom-Sup：60 ns
传播延迟（tpd）：70 ns认证状态：Not Qualified
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：15.24 mm
Base Number Matches：1

M74HCT648B1R 数据手册

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M74HCT646  
M74HCT648  
HCT646 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE)  
HCT648 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.)  
.
HIGH SPEED  
MAX = 60 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
CC = 4 µA (MAX.) AT TA = 25 °C  
COMPATIBLE WITH TTL OUTPUTS  
VIH = 2V (MIN.) VIL = 0.8V (MAX)  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 6 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS646/648  
f
.
.
.
.
.
.
I
B1R  
M1R  
(Plastic Package)  
(Micro Package)  
ORDER CODES :  
M74HCTXXXM1R  
M74HCTXXXB1R  
DESCRIPTION  
The M74HCT646/648 are high speed CMOS  
OCTAL BUS TRANSCEIVERS AND REGISTERS,  
(3-STATE) fabricated in silicon gate C2MOS tech-  
nology. They have the same high speed  
performance of LSTTL combined with true CMOS  
low power consumption. These devices consist of  
bus transceiver circuits with 3-state output, D-type  
flip-flops, and control circuitry arranged for multi-  
plexed transmission of data directly from the input  
bus or from the internal registers. Data on the A or  
B bus will be clocked into the registers on the low-  
to-high transition of the appropriate clock pin (Clock  
AB - or Clock BA). Enable (G) and direction (DIR)  
pins are provided to control the transceiver function-  
s. In the transceiver mode, data present at the  
high-impedance port may bestoredin either register  
or in both. The select controls (Select AB select BA)  
can multiplex stored and real-time (transparent  
mode) data. The direction control determines which  
bus will receive data when enable G is active (low).  
In the isolation mode (enable G high), ”A” data may  
be stored in one register and/or ”B” data may be  
storedin the other register. When anoutput function  
is disabled, the input function is still enabled and  
may be used to store and transmit data. Only one  
of the two buses, A or B, may be driven at a time.  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.This integrated circuit has input and output  
characteristics that are fully compatible with 54/74  
LSTTL logic families. M74HCT devices are de-  
signed to directly interface HSC2MOS systems with  
TTL and NMOS components. They are also plug in  
replacements for LSTTL devices giving a reduction  
of power consumption.  
PIN CONNECTIONS (top view)  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
GAB, GAB, CAB,  
SAB, SBA, CBA  
A, B  
October 1993  
1/12  
1234567...12

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