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M74HC366M1R PDF预览

M74HC366M1R

更新时间: 2024-11-24 22:19:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
11页 251K
描述
HEX BUS BUFFER 3-STATE HC365 NON INVERTING- HC366 INVERTING

M74HC366M1R 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.31其他特性:WITH DUAL OUTPUT ENABLE
控制类型:ENABLE LOW系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.9 mm负载电容(CL):150 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.006 A
湿度敏感等级:3位数:6
功能数量:1端口数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):260
电源:2/6 VProp。Delay @ Nom-Sup:27 ns
传播延迟(tpd):195 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
Base Number Matches:1

M74HC366M1R 数据手册

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M54/M74HC365  
M54/M74HC366  
HEX BUS BUFFER (3-STATE)  
HC365 NON INVERTING - HC366 INVERTING  
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HIGH SPEED  
tPD = 9 ns (TYP) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 6 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS365/366  
ORDER CODES :  
M54HCXXXF1R  
M74HCXXXB1R  
M74HCXXXM1R  
M74HCXXXC1R  
PIN CONNECTIONS (top view)  
HC365  
DESCRIPTION  
The M54/74HC365 and the M54/74HC366 are high  
speed CMOS HEX BUS BUFFER fabricated in sili-  
con gate C2MOS technology. They have the same  
high speed performance of LSTTL combined with  
true CMOS low power consumption.  
HC366  
All six buffers are controlled by the combination of  
two enable inputs (G1 and G2) ; all outputs of these  
buffers are enabled only when both G1 and G2 in-  
puts are held low, under all other conditions these  
output are disabled to be high-impedance.  
Theseoutputs are capable of driving upto15LSTTL  
loads. The designer has a choice of non-inverting  
outputs (HC365) and inverting outputs (HC366). All  
inputs are equipped with protection circuits against  
static discharge and transient excess voltage.  
October 1992  
1/11  

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