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M74HC373 PDF预览

M74HC373

更新时间: 2024-11-03 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输出元件
页数 文件大小 规格书
13页 273K
描述
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC373 NON INVERTING - HC533 INVERTING

M74HC373 数据手册

 浏览型号M74HC373的Datasheet PDF文件第2页浏览型号M74HC373的Datasheet PDF文件第3页浏览型号M74HC373的Datasheet PDF文件第4页浏览型号M74HC373的Datasheet PDF文件第5页浏览型号M74HC373的Datasheet PDF文件第6页浏览型号M74HC373的Datasheet PDF文件第7页 
M54/74HC373  
M54/74HC533  
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT  
HC373 NON INVERTING - HC533 INVERTING  
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HIGH SPEED  
PD = 11 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
t
V
NIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOL = IOH = 6 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
VCC (OPR) = 2 V TO 6 V  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS373/533  
ORDER CODES :  
M54HCXXXF1R  
M74HCXXXB1R  
M74HCXXXM1R  
M74HCXXXC1R  
DESCRIPTION  
The M54/74HC373/533 are high speed CMOS  
OCTAL LATCH WITH 3-STATE OUTPUTS  
fabricated with in silicon gate C2MOS technology.  
of D input data. While the OE input is at low level,  
the eight outputs will be in a normal logic state (high  
or low logic level) and while high level the outpts will  
be in a high impedance state.  
These ICs achive the high speed operation similar  
to equivalent LSTTL while maintaning the CMOS  
low power dissipation.  
The application designer has  
a choise of  
combination of inverting and non inverting outputs.  
These 8 bit D-Type latches are controlled by a latch  
enable input (LE) and a output enable input (OE).  
The three state output configuration and the wide  
choise of outline make bus organized system  
simple.  
While the LE input is held at a high level, the Q  
outputs will follow the data input precisely or  
inversely. When the LE is taken low, the Q outputs  
will be latched precisely or inversely at the logic level  
All inputs are equipped with protection circuits  
against discharge and transient excess voltage.  
PIN CONNECTION (top view)  
HC373  
HC533  
HC373  
HC533  
October 1993  
1/13  

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OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC373 NON INVERTING - HC533 INVERTING
M74HC373C1R STMICROELECTRONICS

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OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC373 NON INVERTING - HC533 INVERTING
M74HC373F1R STMICROELECTRONICS

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OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC373 NON INVERTING - HC533 INVERTING
M74HC373M1R STMICROELECTRONICS

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OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC373 NON INVERTING - HC533 INVERTING
M74HC373RM13T STMICROELECTRONICS

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OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC373 NON INVERTING - HC533 INVERTING
M74HC373RM13TR STMICROELECTRONICS

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OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC373 NON INVERTING - HC533 INVERTING
M74HC373TTR STMICROELECTRONICS

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OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING
M74HC374 STMICROELECTRONICS

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OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HC374 NON INVERTING - HC534 INVERTING
M74HC374B1R STMICROELECTRONICS

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OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HC374 NON INVERTING - HC534 INVERTING
M74HC374C1R STMICROELECTRONICS

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OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HC374 NON INVERTING - HC534 INVERTING