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M74HC368M1 PDF预览

M74HC368M1

更新时间: 2024-11-21 13:10:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
10页 242K
描述
HC/UH SERIES, 6-BIT DRIVER, INVERTED OUTPUT, PDSO16, MICRO, PLASTIC, DIP-16

M74HC368M1 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:MICRO, PLASTIC, DIP-16针数:16
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.28Is Samacsys:N
其他特性:ONE FUNCTION WITH TWO BITS控制类型:ENABLE LOW
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.006 A位数:6
功能数量:1端口数量:2
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
Prop。Delay @ Nom-Sup:30 ns传播延迟(tpd):29 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

M74HC368M1 数据手册

 浏览型号M74HC368M1的Datasheet PDF文件第2页浏览型号M74HC368M1的Datasheet PDF文件第3页浏览型号M74HC368M1的Datasheet PDF文件第4页浏览型号M74HC368M1的Datasheet PDF文件第5页浏览型号M74HC368M1的Datasheet PDF文件第6页浏览型号M74HC368M1的Datasheet PDF文件第7页 
M74HC368  
HEX BUS BUFFER  
WITH 3 STATE OUTPUT INVERTING  
HIGH SPEED:  
= 9ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 6mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC368B1R  
M74HC368M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 368  
M74HC368RM13TR  
M74HC368TTR  
TSSOP  
DESCRIPTION  
The M74HC368 is an high speed CMOS HEX  
BUS BUFFER 3-STATE OUTPUTS fabricated  
with silicon gate C MOS technology.  
enabled when G1 and/or G2 inputs are held low,  
and when held high, these outputs are disabled in  
a high-impedance state.  
2
This device contains six buffers, four buffers are  
controlled by an enable input (G1) and the other  
two buffers are controlled by the other enable  
input (G2); the outputs of each buffer group are  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/10  

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