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M74HC373RM13TR PDF预览

M74HC373RM13TR

更新时间: 2024-11-03 22:14:43
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 逻辑集成电路光电二极管输出元件驱动
页数 文件大小 规格书
13页 273K
描述
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC373 NON INVERTING - HC533 INVERTING

M74HC373RM13TR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.2Is Samacsys:N
系列:HC/UHJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.006 A湿度敏感等级:3
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:2/6 V
Prop。Delay @ Nom-Sup:31 ns传播延迟(tpd):265 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:7.5 mmBase Number Matches:1

M74HC373RM13TR 数据手册

 浏览型号M74HC373RM13TR的Datasheet PDF文件第2页浏览型号M74HC373RM13TR的Datasheet PDF文件第3页浏览型号M74HC373RM13TR的Datasheet PDF文件第4页浏览型号M74HC373RM13TR的Datasheet PDF文件第5页浏览型号M74HC373RM13TR的Datasheet PDF文件第6页浏览型号M74HC373RM13TR的Datasheet PDF文件第7页 
M54/74HC373  
M54/74HC533  
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT  
HC373 NON INVERTING - HC533 INVERTING  
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HIGH SPEED  
PD = 11 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
t
V
NIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOL = IOH = 6 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
VCC (OPR) = 2 V TO 6 V  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS373/533  
ORDER CODES :  
M54HCXXXF1R  
M74HCXXXB1R  
M74HCXXXM1R  
M74HCXXXC1R  
DESCRIPTION  
The M54/74HC373/533 are high speed CMOS  
OCTAL LATCH WITH 3-STATE OUTPUTS  
fabricated with in silicon gate C2MOS technology.  
of D input data. While the OE input is at low level,  
the eight outputs will be in a normal logic state (high  
or low logic level) and while high level the outpts will  
be in a high impedance state.  
These ICs achive the high speed operation similar  
to equivalent LSTTL while maintaning the CMOS  
low power dissipation.  
The application designer has  
a choise of  
combination of inverting and non inverting outputs.  
These 8 bit D-Type latches are controlled by a latch  
enable input (LE) and a output enable input (OE).  
The three state output configuration and the wide  
choise of outline make bus organized system  
simple.  
While the LE input is held at a high level, the Q  
outputs will follow the data input precisely or  
inversely. When the LE is taken low, the Q outputs  
will be latched precisely or inversely at the logic level  
All inputs are equipped with protection circuits  
against discharge and transient excess voltage.  
PIN CONNECTION (top view)  
HC373  
HC533  
HC373  
HC533  
October 1993  
1/13  

M74HC373RM13TR 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC373M TI

类似代替

High Speed CMOS Logic Octal Transparent Latch, Three-State Output
MC74HC373ADWG ONSEMI

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Octal 3−State Non−Inverting Transparent Latch High−Performance Silicon&#
SN74HC373DW TI

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