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M74HC368M1R PDF预览

M74HC368M1R

更新时间: 2024-11-24 22:19:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 252K
描述
HEX BUS BUFFER 3-STATE HC367 NON INVERTING, HC368 INVERTING

M74HC368M1R 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.26
Is Samacsys:N其他特性:ONE FUNCTION WITH TWO BITS
控制类型:ENABLE LOW系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.9 mm负载电容(CL):150 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.006 A
湿度敏感等级:1位数:6
功能数量:1端口数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:2/6 V
Prop。Delay @ Nom-Sup:26 ns传播延迟(tpd):160 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

M74HC368M1R 数据手册

 浏览型号M74HC368M1R的Datasheet PDF文件第2页浏览型号M74HC368M1R的Datasheet PDF文件第3页浏览型号M74HC368M1R的Datasheet PDF文件第4页浏览型号M74HC368M1R的Datasheet PDF文件第5页浏览型号M74HC368M1R的Datasheet PDF文件第6页浏览型号M74HC368M1R的Datasheet PDF文件第7页 
M54/M74HC367  
M54/M74HC368  
HEX BUS BUFFER (3-STATE)  
HC367 NON INVERTING, HC368 INVERTING  
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HIGH SPEED  
tPD = 11 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 6 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS367/368  
ORDER CODES :  
M54HCXXXF1R  
M74HCXXXB1R  
M74HCXXXM1R  
M74HCXXXC1R  
PIN CONNECTIONS (top view)  
HC368  
DESCRIPTION  
The M54/74HC367 and the M54/74HC368 are high  
speed CMOS HEX BUS BUFFER (3-STATE) fabri-  
cated in silicon gate C2MOS technology. They have  
the same high speed performance of LSTTL com-  
bined with true CMOS low power consumption.  
These devices contain six buffers, four buffers are  
controlled by an enable input (G1) and the other two  
buffers are controlled by the other enable input  
(G2) ; the outputs of each buffer group are enabled  
when G1 and/or G2 inputs are held low, and  
when held high these outputs are disabled to be  
high-impedance.  
HC367  
Theseoutputs are capable of driving upto15LSTTL  
loads. The designer has a choice of non-inverting  
outputs (HC367) and inverting outputs (HC368).  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
October 1992  
1/11  

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