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M74HC237C1R PDF预览

M74HC237C1R

更新时间: 2024-11-01 22:37:15
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 解码器驱动器逻辑集成电路输入元件双倍数据速率
页数 文件大小 规格书
11页 259K
描述
3 TO 8 LINE DECODER LATCH

M74HC237C1R 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:CC-20
针数:20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.84其他特性:ADDRESS LATCHES; 2 ENABLE INPUTS
系列:HC/UHJESD-30 代码:S-PQCC-J20
JESD-609代码:e3长度:8.9662 mm
负载电容(CL):50 pF逻辑集成电路类型:OTHER DECODER/DRIVER
最大I(ol):0.004 A功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC20,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 VProp。Delay @ Nom-Sup:45 ns
传播延迟(tpd):45 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Decoder/Drivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8.9662 mm
Base Number Matches:1

M74HC237C1R 数据手册

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M54HC237  
M74HC237  
3 TO 8 LINE DECODER LATCH  
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HIGH SPEED  
tPD = 12 ns (TYP.) at VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS237  
ORDER CODES :  
M54HC237F1R  
M74HC237B1R  
M74HC237M1R  
M74HC237C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC237 is a high speed CMOS 3 TO 8  
LINE DECODER LATCH fabricated in silicon gate  
C2MOS technology.  
It has the same high speed performance of LSTTL  
combined with true CMOS low power consumption.  
When GL goes from low to high, the address present  
at the select inputs (A, B, C) is stored in the latches.  
As long as GL remains high no address changes will  
be recognized. Output enable controls, G1 and G2  
control the state of the outputs independantly of the  
select or latch-enable inputs. All of the outputs are low  
unless G1 is high and G2 is low. The ’HC237 is ideally  
suited for the implementation of glitch-free decoders  
in stored-address applications in bus oriented sys-  
tems. All inputs are equipped with protection circuits  
against static discharge and transient excess voltage.  
NC =  
No Internal  
Connection  
October 1992  
1/11  

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