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M74HC237TTR PDF预览

M74HC237TTR

更新时间: 2024-11-02 03:09:47
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
11页 182K
描述
3 TO 8 LINE DECODER LATCH

M74HC237TTR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP16,.25
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.56系列:HC/UH
输入调节:STANDARDJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:OTHER DECODER/DRIVER
最大I(ol):0.004 A功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
Prop。Delay @ Nom-Sup:54 ns传播延迟(tpd):270 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Decoder/Drivers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

M74HC237TTR 数据手册

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M74HC237  
3 TO 8 LINE DECODER LATCH  
HIGH SPEED:  
= 16ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC237B1R  
M74HC237M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 237  
M74HC237RM13TR  
M74HC237TTR  
TSSOP  
DESCRIPTION  
The M74HC237 is an high speed CMOS 3 TO 8  
LINE DECODER fabricated with silicon gate  
C MOS technology.  
latch-enable inputs. All of the outputs are low  
unless G1 is high and G2 is low. The M74HC237  
is ideally suited for the implementation of  
2
When GL goes from low to high, the address  
present at the select inputs (A, B, C) is stored in  
the latches. As long as GL remains high no  
address changes will be recognized. Output  
enable controls, G1 and G2 control the state of the  
outputs independently of the select or  
glitch-free  
decoders  
in  
stored-address  
applications in bus oriented systems.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/11  

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