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M74HC240C1R PDF预览

M74HC240C1R

更新时间: 2024-11-01 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输出元件
页数 文件大小 规格书
12页 272K
描述
HC240: INVERTED - HC241/244 NON INVERTED OCTAL BUS BUFFER WITH 3 STATE OUTPUTS

M74HC240C1R 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QLCC包装说明:PLASTIC, LCC-20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.77
控制类型:ENABLE LOW系列:HC/UH
JESD-30 代码:S-PQCC-J20JESD-609代码:e3
长度:8.965 mm负载电容(CL):150 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.006 A
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC20,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 VProp。Delay @ Nom-Sup:23 ns
传播延迟(tpd):33 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8.965 mm
Base Number Matches:1

M74HC240C1R 数据手册

 浏览型号M74HC240C1R的Datasheet PDF文件第2页浏览型号M74HC240C1R的Datasheet PDF文件第3页浏览型号M74HC240C1R的Datasheet PDF文件第4页浏览型号M74HC240C1R的Datasheet PDF文件第5页浏览型号M74HC240C1R的Datasheet PDF文件第6页浏览型号M74HC240C1R的Datasheet PDF文件第7页 
M54HC240/241/244  
M74HC240/241/244  
OCTAL BUS BUFFER WITH 3 STATE OUTPUTS  
HC240: INVERTED - HC241/244 NON INVERTED  
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HIGH SPEED  
PD = 10 ns (TYP.) at VCC = 5V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) at TA = 25 oC  
HIGH NOISE IMMUNITY  
t
V
NIH = VINL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 6 mA (MIN)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
VCC (OPR) = 2V to 6V  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS240/241/244  
ORDER CODES :  
M54HCXXXF1R  
M74HCXXXB1R  
M74HCXXXM1R  
M74HCXXXC1R  
DESCRIPTION  
The M54/74HC240, HC241 and HC244 are high  
speed CMOS OCTAL BUS BUFFERs fabricated in  
silicon gate C2MOS technology.  
complementary G and G inputs. Each control input  
governs four BUS BUFFERs.  
These devices are designed to be used with 3 state  
memory address drivers, etc. All inputs are  
equipped with protection circuits against static  
discharge and transient excess voltage.  
They have the same high speed performance of  
LSTTL combined with true CMOS low power  
consumption.  
The designer has a choise of select combination of  
inverting and non-inverting outputs, symmetrical G  
(active low output  
control) input, and  
PIN CONNECTION (top view)  
HC240  
HC241  
HC244  
October 1993  
1/12  

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OCTAL BUS BUFFER WITH 3 STATE OUTPUTS HC240HV: INVERTED - HC241HV NON INVERTED
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HC240: INVERTED - HC241/244 NON INVERTED OCTAL BUS BUFFER WITH 3 STATE OUTPUTS
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OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (INVERTED)
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OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (INVERTED)
M74HC241 STMICROELECTRONICS

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HC240: INVERTED - HC241/244 NON INVERTED OCTAL BUS BUFFER WITH 3 STATE OUTPUTS