Datasheet > M74HC237M1R

M74HC237M1R

更新时间： 2024-11-01 22:57:55

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
11页	259K
描述
3 TO 8 LINE DECODER LATCH

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中文翻译

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数据手册

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M74HC237M1R 数据手册

M54HC237

M74HC237

3 TO 8 LINE DECODER LATCH

HIGH SPEED

t_PD= 12 ns (TYP.) at V_CC= 5 V

LOW POWER DISSIPATION

I_CC= 4 µA (MAX.) AT T_A= 25 °C

HIGH NOISE IMMUNITY

V_NIH= V_NIL= 28 % V_CC(MIN.)

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

SYMMETRICAL OUTPUT IMPEDANCE

I_OH= I_OL= 4 mA (MIN.)

BALANCED PROPAGATION DELAYS

t_PLH= t_PHL

WIDE OPERATING VOLTAGE RANGE

B1R

(Plastic Package)

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

V_CC(OPR) = 2 V TO 6 V

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS237

ORDER CODES :

M54HC237F1R

M74HC237B1R

M74HC237M1R

M74HC237C1R

PIN CONNECTIONS (top view)

DESCRIPTION

The M54/74HC237 is a high speed CMOS 3 TO 8

LINE DECODER LATCH fabricated in silicon gate

C²MOS technology.

It has the same high speed performance of LSTTL

combined with true CMOS low power consumption.

When GL goes from low to high, the address present

at the select inputs (A, B, C) is stored in the latches.

As long as GL remains high no address changes will

be recognized. Output enable controls, G1 and G2

control the state of the outputs independantly of the

select or latch-enable inputs. All of the outputs are low

unless G1 is high and G2 is low. The ’HC237 is ideally

suited for the implementation of glitch-free decoders

in stored-address applications in bus oriented sys-

tems. All inputs are equipped with protection circuits

against static discharge and transient excess voltage.

NC =

No Internal

Connection

October 1992

1/11

12 3 4 5 6 7...11

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