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M74HC137M1R PDF预览

M74HC137M1R

更新时间: 2024-11-22 22:46:35
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 解码器驱动器锁存器逻辑集成电路光电二极管输入元件双倍数据速率
页数 文件大小 规格书
11页 258K
描述
3 TO 8 LINE DECODER/LATCH INVERTING

M74HC137M1R 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SO-16针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.16
Is Samacsys:N其他特性:ADDRESS LATCHES; 2 ENABLE INPUTS
系列:HC/UH输入调节:STANDARD
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.9 mm负载电容(CL):50 pF
逻辑集成电路类型:OTHER DECODER/DRIVER最大I(ol):0.004 A
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 VProp。Delay @ Nom-Sup:22 ns
传播延迟(tpd):110 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Decoder/Drivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

M74HC137M1R 数据手册

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M54HC137  
M74HC137  
3 TO 8 LINE DECODER/LATCH (INVERTING)  
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HIGH SPEED  
tPD = 11 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS137  
ORDER CODES :  
M54HC137F1R  
M74HC137B1R  
M74HC137M1R  
M74HC137C1R  
DESCRIPTION  
The M54/74HC137 is a high speed CMOS 3 TO 8LINE  
DECODER/LATCH (INVERTING) fabricated in silicon  
gate C2MOS technology. It has the same high speed  
performance of LSTTL combined with true CMOS low  
power consumption. This device is a 3 to 8line decoder  
withlatches on thethree address inputs. When GL goes  
from low tohigh, theaddress present at theselect inputs  
(A, B and C) is stored in the latches. As long as GL re-  
mains high no address changes will be recognized. Out-  
put enable pins G1 and G2, control the state of the  
outputs independently of the select or latch-enable in-  
puts. All the outputs are high unless G1 is high and G2  
is low. The HC137 is ideally suited for the implementa-  
tion of glitch-free decoders in stored-address applica-  
tions in bus oriented systems. All inputs are equipped  
withprotection circuits against staticdischarge and tran-  
sient excess voltage.  
PIN CONNECTIONS (top view)  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
February 1993  
1/11  

M74HC137M1R 替代型号

型号 品牌 替代类型 描述 数据表
TC74HC137AF-TP2EL TOSHIBA

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IC HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16, 0.300 INCH, PLASTIC, SOIC-

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