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M74HC137RM13TR PDF预览

M74HC137RM13TR

更新时间: 2024-09-13 21:11:15
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 驱动双倍数据速率输入元件光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
11页 78K
描述
HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16, SO-16

M74HC137RM13TR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.17其他特性:ADDRESS LATCHES; 2 ENABLE INPUTS
系列:HC/UH输入调节:STANDARD
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9 mm负载电容(CL):50 pF
逻辑集成电路类型:OTHER DECODER/DRIVER最大I(ol):0.004 A
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL电源:2/6 V
Prop。Delay @ Nom-Sup:22 ns传播延迟(tpd):110 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Decoder/Drivers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
Base Number Matches:1

M74HC137RM13TR 数据手册

 浏览型号M74HC137RM13TR的Datasheet PDF文件第2页浏览型号M74HC137RM13TR的Datasheet PDF文件第3页浏览型号M74HC137RM13TR的Datasheet PDF文件第4页浏览型号M74HC137RM13TR的Datasheet PDF文件第5页浏览型号M74HC137RM13TR的Datasheet PDF文件第6页浏览型号M74HC137RM13TR的Datasheet PDF文件第7页 
M74HC137  
3 TO 8 LINE DECODER/LATCH (INVERTING)  
HIGH SPEED:  
=18ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 2µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC137B1R  
M74HC137M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 137  
M74HC137RM13TR  
M74HC137TTR  
TSSOP  
DESCRIPTION  
The M74HC137 is an high speed CMOS 3 TO 8  
LINE DECODER/LATCH (INVERTING) fabricated  
with silicon gate C MOS technology.  
This device is a 3 to 8 line decoder with latches on  
the three address inputs. When GL goes from low  
to high, the addresses present at the select inputs  
(A, B, and C) is stored in the latches. As long as  
GL remains high no address changes will be  
recognized. Output enable pins G1 and G2,  
control the state of the outputs independently of  
the select or latch-enable inputs. All the outputs  
are high unless G1 is high and G2 is low. The  
74HC137 is ideally suited for the implementation  
of glitch-free decoders in stored-address  
application in bus oriented systems.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
2
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/11  

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