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M27V512-200N1TR PDF预览

M27V512-200N1TR

更新时间: 2024-10-28 22:35:03
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 存储内存集成电路光电二极管可编程只读存储器OTP只读存储器电动程控只读存储器
页数 文件大小 规格书
16页 110K
描述
512 Kbit 64Kb x8 Low Voltage UV EPROM and OTP EPROM

M27V512-200N1TR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP包装说明:8 X 13.40 MM, PLASTIC, TSOP-28
针数:28Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.92Is Samacsys:N
最长访问时间:200 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:11.8 mm内存密度:524288 bit
内存集成电路类型:OTP ROM内存宽度:8
功能数量:1端子数量:28
字数:65536 words字数代码:64000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LSSOP封装等效代码:TSSOP28,.53,22
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.25 mm最大待机电流:0.00001 A
子类别:OTP ROMs最大压摆率:0.01 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.55 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8 mm
Base Number Matches:1

M27V512-200N1TR 数据手册

 浏览型号M27V512-200N1TR的Datasheet PDF文件第2页浏览型号M27V512-200N1TR的Datasheet PDF文件第3页浏览型号M27V512-200N1TR的Datasheet PDF文件第4页浏览型号M27V512-200N1TR的Datasheet PDF文件第5页浏览型号M27V512-200N1TR的Datasheet PDF文件第6页浏览型号M27V512-200N1TR的Datasheet PDF文件第7页 
M27V512  
512 Kbit (64Kb x8) Low Voltage UV EPROM and OTP EPROM  
LOW VOLTAGE READ OPERATION:  
3V to 3.6V  
FAST ACCESS TIME: 100ns  
LOW POWER CONSUMPTION:  
28  
28  
– Active Current 10mA at 5MHz  
– Standby Current 10µA  
1
1
PROGRAMMING VOLTAGE: 12.75V ± 0.25V  
FDIP28W (F)  
PDIP28 (B)  
PROGRAMMING TIME: 100µs/byte (typical)  
ELECTRONIC SIGNATURE  
– Manufacturer Code: 20h  
– Device Code: 3Dh  
DESCRIPTION  
The M27V512 is a low voltage 512 Kbit EPROM  
offered in the two ranges UV (ultra viloet erase)  
and OTP (one time programmable). It is ideally  
suited for microprocessor systems and is orga-  
nized as 65,536 by 8 bits.  
PLCC32 (K)  
TSOP28 (N)  
8 x 13.4mm  
Figure 1. Logic Diagram  
The M27V512 operates in the read mode with a  
supply voltage as low as 3V. The decrease in op-  
erating power allows either a reduction of the size  
of the battery or an increase in the time between  
battery recharges.  
V
CC  
The FDIP28W (window ceramic frit-seal package)  
has transparent lid which allows the user to ex-  
pose the chip to ultraviolet light to erase the bit pat-  
tern. A new pattern can then be written to the  
device by following the programming procedure.  
For applications where the content is programmed  
only one time and erasure is not required, the  
M27V512 is offered in PDIP28, PLCC32 and  
TSOP28 (8 x 13.4 mm) packages.  
16  
8
A0-A15  
E
Q0-Q7  
M27V512  
GV  
PP  
Table 1. Signal Names  
A0-A15  
Q0-Q7  
E
Address Inputs  
Data Outputs  
Chip Enable  
Output Enable  
Supply Voltage  
Ground  
V
SS  
AI00732B  
GV  
PP  
V
CC  
V
SS  
May 1998  
1/16  

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