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LTC2194 PDF预览

LTC2194

更新时间: 2024-09-18 14:57:51
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 898K
描述
16 位、105Msps、低功率双通道 ADC

LTC2194 数据手册

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LTC2195  
LTC2194/LTC2193  
16-Bit, 125/105/80Msps  
Low Power Dual ADCs  
FEATURES  
DESCRIPTION  
The LTC®2195/LTC2194/LTC2193 are 2-channel, simul-  
taneous sampling 16-bit A/D converters designed for  
digitizing high frequency, wide dynamic range signals.  
They are perfect for demanding communications applica-  
tions with AC performance that includes 76.8dB SNR and  
90dB spurious free dynamic range (SFDR). Ultralow jitter  
n
2-Channel Simultaneous Sampling ADC  
n
Serial LVDS Outputs: 1, 2 or 4 Bits per Channel  
n
76.8dB SNR  
90dB SFDR  
n
n
Low Power: 432mW/360mW/249mW Total  
n
216mW/180mW/125mW per Channel  
n
Single 1.8V Supply  
of0.07ps  
allowsundersamplingofIFfrequencieswith  
RMS  
n
Selectable Input Ranges: 1V to 2V  
excellent noise performance.  
P-P  
P-P  
n
n
n
n
550MHz Full-Power Bandwidth S/H  
DC specs include 2LSB INL (typ), 0.5LSB DNL (typ)  
and no missing codes over temperature. The transition  
Shutdown and Nap Modes  
Serial SPI Port for Configuration  
52-Pin (7mm × 8mm) QFN Package  
noise is 3.4LSB  
.
RMS  
To minimize the number of data lines the digital outputs  
are serial LVDS. Each channel outputs two bits or four bits  
at a time. At lower sampling rates there is a one bit per  
channel option. The LVDS drivers have optional internal  
termination and adjustable output levels to ensure clean  
signal integrity.  
APPLICATIONS  
n
Communications  
n
Cellular Base Stations  
n
Software-Defined Radios  
Portable Medical Imaging  
Multi-Channel Data Acquisition  
n
+
The ENC and ENC inputs may be driven differentially or  
single ended with a sine wave, PECL, LVDS, TTL or CMOS  
inputs. An internal clock duty cycle stabilizer allows high  
performance at full speed for a wide range of clock duty  
cycles.  
n
n
Nondestructive Testing  
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear  
Technology Corporation. All other trademarks are the property of their respective owners.  
TYPICAL APPLICATION  
2-Tone FFT, fIN = 70MHz and 69MHz  
1.8V  
1.8V  
OV  
0
–10  
–20  
–30  
–40  
–50  
V
DD  
DD  
OUT1A  
OUT1B  
OUT1C  
OUT1D  
OUT2A  
OUT2B  
OUT2C  
OUT2D  
CH1  
ANALOG  
INPUT  
16-BIT  
ADC CORE  
S/H  
S/H  
CH2  
ANALOG  
INPUT  
SERIALIZED  
16-BIT  
ADC CORE  
DATA  
SERIALIZER  
–60  
LVDS  
–70  
OUTPUTS  
–80  
–90  
–100  
–110  
–120  
ENCODE  
INPUT  
PLL  
DATA CLOCK OUT  
FRAME  
GND  
OGND  
0
20  
30  
40  
50  
60  
10  
219543 TA01a  
FREQUENCY (MHz)  
219543 TA01b  
219543f  
1

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