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LTC2203

更新时间： 2024-11-08 14:57:35
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
32页 1455K
描述
16 位、25Msps ADC

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中文翻译

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LTC2203 数据手册

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LTC2203/LTC2202  
16-Bit, 25Msps/10Msps ADCs  
FEATURES  
DESCRIPTION  
Sample Rate: 25Msps/10Msps  
The LTC®2203/LTC2202 are 25Msps/10Msps, sampling  
16-bitA/Dconvertersdesignedfordigitizinghighfrequen-  
cy, wide dynamic range signals with input frequencies up  
to 380MHz. The input range of the ADC can be optimized  
with the PGA front end.  
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81.6dB SNR and 100dB SFDR (2.5V Range)  
n
SFDR 90dB at 70MHz (1.667V Input Range)  
PGA Front End (2.5V or 1.667V Input Range)  
380MHz Full Power Bandwidth S/H  
Optional Internal Dither  
Optional Data Output Randomizer  
Single 3.3V Supply  
P-P  
n
n
n
n
n
n
n
n
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P-P  
P-P  
The LTC2203/LTC2202 are perfect for demanding app-  
lications, with AC performance that includes 81.6dB  
SNR and 100dB spurious free dynamic range (SFDR).  
Maximum DC specs include ±±LSB ꢀNL, ±1LSB DNL (no  
missing codes).  
Power Dissipation: 220mW/1±0mW  
Clock Duty Cycle Stabilizer  
Out-of-Range ꢀndicator  
A separate output power supply allows the CMOS output  
swing to range from 0.5V to 3.6V.  
Pin Compatible Family  
25Msps: LTC2203 (16-Bit)  
10Msps: LTC2202 (16-Bit)  
±8-Pin (7mm × 7mm) QFN Package  
Asingle-endedCLKinputcontrolsconverteroperation.An  
optionalclockdutycyclestabilizerallowshighperformance  
at full speed with a wide range of clock duty cycles.  
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear  
Technology Corporation. All other trademarks are the property of their respective owners.  
Protected by U.S. Patents including ±8±3302, 69±9965B1.  
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APPLICATIONS  
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Telecommunications  
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Receivers  
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Cellular Base Stations  
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Spectrum Analysis  
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ꢀmaging Systems  
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ATE  
TYPICAL APPLICATION  
LTC2203: 128K Point FFT,  
fIN = 5.1MHz, –1dBFS, PGA = 0  
3.3V  
0
–10  
–20  
–30  
–±0  
SENSE  
OV  
DD  
1.25V  
COMMON MODE  
BꢀAS VOLTAGE  
ꢀNTERNAL ADC  
REFERENCE  
GENERATOR  
V
0.5V TO 3.6V  
CM  
1μF  
2.2μF  
–50  
–60  
–70  
–80  
OF  
CLKOUT+  
CLKOUT–  
+
A
ꢀN  
+
16-BꢀT  
PꢀPELꢀNED  
ADC CORE  
OUTPUT  
DRꢀVERS  
CORRECTꢀON  
LOGꢀC AND  
SHꢀFT REGꢀSTER  
ANALOG  
ꢀNPUT  
S/H  
AMP  
CMOS  
OUTPUTS  
D15  
•
–90  
–
–
•
A
ꢀN  
–100  
–110  
–120  
–130  
–1±0  
•
D0  
OGND  
CLOCK/DUTY  
CYCLE  
CONTROL  
3.3V  
1μF  
V
DD  
1μF  
1μF  
GND  
0
2
±
6
8
10  
12  
FREQUENCY(MHz)  
22032 TA02  
CLK  
PGA SHDN DꢀTH MODE  
ADC CONTROL ꢀNPUTS  
RAND  
OE  
22032 TA01  
22032fd  
1
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