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LTC2203 PDF预览

LTC2203

更新时间: 2024-09-17 05:43:43
品牌 Logo 应用领域
凌特 - Linear 转换器模数转换器
页数 文件大小 规格书
32页 1646K
描述
16-Bit, 25Msps/10Msps ADCs

LTC2203 数据手册

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LTC2203/LTC2202  
16-Bit, 25Msps/10Msps ADCs  
U
FEATURES  
DESCRIPTIO  
The LTC®2203/LTC2202 are 25Msps/10Msps, sampling  
16-bitA/Dconvertersdesignedfordigitizinghighfrequen-  
cy, wide dynamic range signals with input frequencies up  
to 380MHz. The input range of the ADC can be optimized  
with the PGA front end.  
Sample Rate: 25Msps/10Msps  
81.6dB SNR and 100dB SFDR (2.5V Range)  
SFDR 90dB at 70MHz (1.667V Input Range)  
P-P  
PGA Front End (2.5V or 1.667V Input Range)  
P-P  
P-P  
380MHz Full Power Bandwidth S/H  
Optional Internal Dither  
Optional Data Output Randomizer  
Single 3.3V Supply  
The LTC2203/LTC2202 are perfect for demanding ap-  
plications, with AC performance that includes 81.6dB  
SNR and 100dB spurious free dynamic range (SFDR).  
Maximum DC specs include ±±LSB ꢀNL, ±1LSB DNL (no  
missing codes).  
Power Dissipation: 220mW/1±0mW  
Clock Duty Cycle Stabilizer  
Out-of-Range ꢀndicator  
A separate output power supply allows the CMOS output  
swing to range from 0.5V to 3.6V.  
Pin Compatible Family  
25Msps: LTC2203 (16-Bit)  
10Msps: LTC2202 (16-Bit)  
±8-Pin (7mm × 7mm) QFN Package  
Asingle-endedCLKinputcontrolsconverteroperation.An  
optionalclockdutycyclestabilizerallowshighperformance  
at full speed with a wide range of clock duty cycles.  
U
APPLICATIO S  
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All  
other trademarks are the property of their respective owners. Protected by U.S. Patents  
including ±8±3302 and 69±9965B1  
Telecommunications  
Receivers  
Cellular Base Stations  
Spectrum Analysis  
ꢀmaging Systems  
ATE  
U
TYPICAL APPLICATIO  
LTC2203: 128K Point FFT,  
fIN = 5.1MHz, –1dBFS, PGA = 0  
3.3V  
0
–10  
–20  
–30  
–±0  
SENSE  
OV  
DD  
1.25V  
COMMON MODE  
BꢀAS VOLTAGE  
ꢀNTERNAL ADC  
REFERENCE  
GENERATOR  
V
0.5V TO 3.6V  
CM  
1μF  
2.2μF  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
–120  
–130  
–1±0  
OF  
CLKOUT+  
CLKOUT–  
+
A
ꢀN  
+
16-BꢀT  
PꢀPELꢀNED  
ADC CORE  
OUTPUT  
DRꢀVERS  
CORRECTꢀON  
LOGꢀC AND  
SHꢀFT REGꢀSTER  
ANALOG  
ꢀNPUT  
S/H  
AMP  
CMOS  
OUTPUTS  
D15  
A
ꢀN  
D0  
OGND  
CLOCK/DUTY  
CYCLE  
CONTROL  
3.3V  
1μF  
V
DD  
1μF  
1μF  
GND  
0
2
±
6
8
10  
12  
FREQUENCY(MHz)  
22032 GO7  
CLK  
PGA SHDN DꢀTH MODE  
ADC CONTROL ꢀNPUTS  
RAND  
OE  
22032 TA01  
22032fb  
1

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