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LMK04806BISQX/NOPB

更新时间: 2023-09-03 20:28:22
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页数 文件大小 规格书
140页 2185K
描述
具有双级联 PLL 和集成式 2.5GHz VCO 的低噪声时钟抖动消除器 | NKD | 64 | -40 to 85

LMK04806BISQX/NOPB 数据手册

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LMK04803, LMK04805, LMK04806, LMK04808  
www.ti.com  
SNAS489K MARCH 2011REVISED DECEMBER 2014  
Pin Functions(1) (continued)  
PIN  
I/O  
TYPE  
DESCRIPTION  
NUMBER  
NAME  
19, 20  
21, 22  
23  
CLKout4, CLKout4*  
CLKout5*, CLKout5  
GND  
O
O
Programmable  
Programmable  
PWR  
Clock output 4 (clock group 2).  
Clock output 5 (clock group 2).  
Ground.  
24  
Vcc4  
PWR  
Power supply for digital.  
CLKin1, CLKin1*  
Reference Clock Input Port 1 for PLL1. AC or DC Coupled.  
Feedback input for external clock feedback input (0-delay  
mode). AC or DC Coupled.  
FBCLKin, FBCLKin*  
Fin/Fin*  
25, 26  
I
ANLG  
External VCO input (External VCO mode). AC or DC  
Coupled.  
Programmable status pin, default readback output.  
Programmable to holdover mode indicator. Other options  
available by programming.  
27  
Status_Holdover  
CLKin0, CLKin0*  
I/O  
I
Programmable  
ANLG  
Reference Clock Input Port 0 for PLL1.  
AC or DC Coupled.  
28, 29  
30  
Vcc5  
PWR  
Power supply for clock inputs and OSCout1.  
Buffered output 1 of OSCin port.  
31, 32  
OSCout1, OSCout1*  
O
I/O  
O
LVPECL  
Programmable status pin, default lock detect for PLL1 and  
PLL2. Other options available by programming.  
33  
Status_LD  
Programmable  
34  
35  
CPout1  
Vcc6  
ANLG  
PWR  
Charge pump 1 output.  
Power supply for PLL1, charge pump 1.  
Feedback to PLL1, Reference input to PLL2.  
AC Coupled.  
36, 37  
OSCin, OSCin*  
I
ANLG  
38  
Vcc7  
PWR  
Power supply for OSCin, OSCout0, and PLL2 circuitry.(2)  
Buffered output 0 of OSCin port.(2)  
Power supply for PLL2, charge pump 2.  
Charge pump 2 output.  
39, 40  
41  
OSCout0, OSCout0*  
Vcc8  
O
O
Programmable  
PWR  
42  
CPout2  
ANLG  
43  
Vcc9  
PWR  
Power supply for PLL2.  
44  
LEuWire  
I
I
I
CMOS  
MICROWIRE Latch Enable Input.  
45  
CLKuWire  
CMOS  
MICROWIRE Clock Input.  
46  
DATAuWire  
Vcc10  
CMOS  
MICROWIRE Data Input.  
47  
PWR  
Power supply for clock group 3: CLKout6 and CLKout7.  
Clock output 6 (clock group 3).  
48, 49  
50, 51  
52  
CLKout6, CLKout6*  
CLKout7*, CLKout7  
Vcc11  
O
O
Programmable  
Programmable  
PWR  
Clock output 7 (clock group 3).  
Power supply for clock group 4: CLKout8 and CLKout9.  
Clock output 8 (clock group 4).  
53, 54  
55, 56  
57  
CLKout8, CLKout8*  
CLKout9*, CLKout9  
Vcc12  
O
O
Programmable  
Programmable  
PWR  
Clock output 9 (clock group 4).  
Power supply for clock group 5: CLKout10 and CLKout11.  
CLKout10,  
CLKout10*  
58, 59  
60, 61  
O
O
Programmable  
Programmable  
Clock output 10 (clock group 5).  
Clock output 11 (clock group 5).  
CLKout11*,  
CLKout11  
Programmable status pin. Default is input for pin control of  
PLL1 reference clock selection. CLKin0 LOS status and  
other options available by programming.  
62  
63  
Status_CLKin0  
Status_CLKin1  
I/O  
I/O  
Programmable  
Programmable  
Programmable status pin. Default is input for pin control of  
PLL1 reference clock selection. CLKin1 LOS status and  
other options available by programming.  
64  
Vcc13  
DAP  
PWR  
GND  
Power supply for clock group 0: CLKout0 and CLKout1.  
DIE ATTACH PAD, connect to GND.  
DAP  
(2) See Vcc5 (CLKin and OSCout1), Vcc7 (OSCin and OSCout0) for information on configuring device for optimum performance.  
Copyright © 2011–2014, Texas Instruments Incorporated  
Submit Documentation Feedback  
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Product Folder Links: LMK04803 LMK04805 LMK04806 LMK04808  
 

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