Datasheet > LMK04828B

LMK04828B

更新时间： 2024-11-05 12:02:39

品牌	Logo	应用领域
德州仪器 - TI		时钟
页数	文件大小	规格书
101页	2232K
描述
LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs

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LMK04828B 数据手册

LMK04826B, LMK04828B

www.ti.com

SNAS605 AP –MARCH 2013–REVISED JUNE 2013

LMK0482xB

Ultra Low-Noise JESD204B Compliant

Clock Jitter Cleaner with Dual Loop PLLs

Check for Samples: LMK04826B, LMK04828B

1 INTRODUCTION

1.1 Features

– Integrated Low-Noise Crystal Oscillator

• JEDEC JESD204B Support

Circuit

• Ultra-Low RMS Jitter and Performance

– 88 fs RMS jitter (12 kHz to 20 MHz)

– 91 fs RMS jitter (100 Hz to 20 MHz)

– –162.5 dBc/Hz noise floor at 245.76 MHz

• Up to 14 Differential Device Clocks from PLL2

– Up to 7 SYSREF Clocks

– Holdover mode when input clocks are lost

• PLL2

– Normalized [1 Hz] PLL noise floor of

–227 dBc/Hz

– Phase detector rate up to 155 MHz

– OSCin frequency-doubler

– Maximum clock output frequency 3.1 GHz

– LVPECL, LVDS, HSDS, LCPECL

programmable outputs from PLL2

– Two Integrated Low-Noise VCOs

• 50% duty cycle output divides, 1 to 32 (even

and odd)

• Precision digital delay, dynamically adjustable

• 25 ps step analog delay

• Multi-mode: Dual PLL, single PLL, and clock

distribution in 0 delay option

• Industrial Temperature Range: –40 to 85°C

• 3.15 V to 3.45 V operation

• Up to 1 buffered VCXO/Crystal output from

PLL1

– LVPECL, LVDS, 2xLVCMOS programmable

• Dual Loop PLLatinum™ PLL Architecture

• PLL1

– Up to 3 redundant input clocks

•

Automatic and manual switch-over

modes

• Package: 64-pin QFN (9.0 x 9.0 x 0.8 mm)

Device

VCO0 Frequency

VCO1 Frequency

•

Hitless switching and LOS

LMK04826

1840 to 1970 MHz

2440 to 2505 MHz

2370 to

2630 MHz

LMK04828

2920 to 3080 MHz

Crystal or

VCXO

OSCout

Multiple —clean“

clocks at different

frequencies

LMX2581

PLL+VCO

Recovered

—dirty“ clock or

clean clock

CLKin0

DCLKout12

Backup

Reference

Clock

FPGA

SDCLKout13

LMK0482xB

CLKin1

DCLKout8 &

DCLKout10

SDCLKout9 &

SDCLKout11

DCLKout4,

SDCLKout5

DCLKout0 &

DCLKout2

DAC

ADC

SDCLKout1 &

SDCLKout3

Serializer/

Deserializer

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PLLatinum is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

12 3 4 5 6 7...101

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与LMK04828B相关器件

型号	品牌	获取价格	描述	数据表
LMK04828BISQ	TI	获取价格	IC OTHER CLOCK GENERATOR, Clock Generator
LMK04828BISQ/NOPB	TI	获取价格	LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs
LMK04828BISQE/NOPB	TI	获取价格	LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs
LMK04828BISQX/NOPB	TI	获取价格	LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs
LMK04828-EP	TI	获取价格	温度范围为 -55°C 至 105°C 且符合 JESD204B 标准的超低噪声时钟抖动消
LMK04828SNKDREP	TI	获取价格	温度范围为 -55°C 至 105°C 且符合 JESD204B 标准的超低噪声时钟抖动消
LMK04828SNKDTEP	TI	获取价格	温度范围为 -55°C 至 105°C 且符合 JESD204B 标准的超低噪声时钟抖动消
LMK04832	TI	获取价格	具有双环路且符合 JESD204B 标准的超低噪声 3.2GHz、15 路输出时钟抖动清除
LMK04832MPAPSEP	TI	获取价格	耐辐射且符合 JESD204C 标准的 30krad 超低噪声 3.2GHz、15 路输出
LMK04832NKDR	TI	获取价格	具有双环路且符合 JESD204B 标准的超低噪声 3.2GHz、15 路输出时钟抖动清除

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