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KM23C4000D-8 PDF预览

KM23C4000D-8

更新时间: 2024-11-30 15:36:23
品牌 Logo 应用领域
三星 - SAMSUNG 有原始数据的样本ROM光电二极管内存集成电路
页数 文件大小 规格书
4页 89K
描述
MASK ROM, 512KX8, 80ns, CMOS, PDIP32, 0.600 INCH, DIP-32

KM23C4000D-8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP32,.6
针数:32Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.89最长访问时间:80 ns
JESD-30 代码:R-PDIP-T32JESD-609代码:e0
长度:41.91 mm内存密度:4194304 bit
内存集成电路类型:MASK ROM内存宽度:8
功能数量:1端子数量:32
字数:524288 words字数代码:512000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512KX8
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP32,.6封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified座面最大高度:5.08 mm
最大待机电流:0.00005 A子类别:MASK ROMs
最大压摆率:0.05 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:15.24 mmBase Number Matches:1

KM23C4000D-8 数据手册

 浏览型号KM23C4000D-8的Datasheet PDF文件第2页浏览型号KM23C4000D-8的Datasheet PDF文件第3页浏览型号KM23C4000D-8的Datasheet PDF文件第4页 
KM23C4000D(G)  
CMOS MASK ROM  
4M-Bit (512Kx8) CMOS MASK ROM  
FEATURES  
GENERAL DESCRIPTION  
· 524,288x8 bit organization  
· Access time : 80ns(Max.)  
· Supply voltage : single +5V  
· Current consumption  
Operating : 50mA(Max.)  
Standby : 50mA(Max.)  
· Fully static operation  
· All inputs and outputs TTL compatible  
· Three state outputs  
· Package  
The KM23C4000D(G) is a fully static mask programmable  
ROM organized 524,288 x 8 bit. It is fabricated using silicon  
gate CMOS process technology.  
This device operates with a 5V single power supply, and all  
inputs and outputs are TTL compatible.  
Because of its asynchronous operation, it requires no external  
clock assuring extremely easy operation.  
It is suitable for use in program memory of microprocessor, and  
data memory, character generator.  
The KM23C4000D is packaged in  
KM23C4000DG in a 32-SOP.  
a
32-DIP and the  
-. KM23C4000D : 32-DIP-600  
-. KM23C4000DG : 32-SOP-525  
FUNCTIONAL BLOCK DIAGRAM  
PIN CONFIGURATION  
A18  
X
MEMORY CELL  
MATRIX  
BUFFERS  
AND  
.
.
.
.
.
.
.
.
N.C  
A16  
A15  
A12  
A7  
1
2
VCC  
32  
(524,288x8)  
31 A18  
DECODER  
A17  
30  
3
A14  
29  
4
Y
A13  
A8  
5
28  
27  
26  
25  
24  
SENSE AMP.  
BUFFERS  
BUFFERS  
AND  
A6  
6
A5  
A9  
7
DIP  
&
DECODER  
A0  
A4  
8
A11  
SOP  
A3  
9
OE  
.
. .  
A2  
10  
23 A10  
21 CE  
A1  
11  
12  
13  
14  
CE  
OE  
Q0  
Q7  
CONTROL  
LOGIC  
A0  
Q7  
Q6  
21  
20  
Q0  
Q1  
Q2  
VSS  
19 Q5  
Q4  
Q3  
15  
16  
18  
17  
Pin Name  
A0 - A18  
Q0 - Q7  
CE  
Pin Function  
Address Inputs  
Data Outputs  
Chip Enable  
Output Enable  
Power(+5V)  
Ground  
KM23C4000D(G)  
OE  
VCC  
VSS  
N.C  
No Connection  

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