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K6R1008V1B-TI8T PDF预览

K6R1008V1B-TI8T

更新时间: 2024-01-01 22:42:16
品牌 Logo 应用领域
三星 - SAMSUNG 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
9页 184K
描述
Standard SRAM, 128KX8, 8ns, CMOS, PDSO32

K6R1008V1B-TI8T 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:TSOP, TSOP32,.46Reach Compliance Code:unknown
风险等级:5.92最长访问时间:8 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G32
JESD-609代码:e0内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
端子数量:32字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP
封装等效代码:TSOP32,.46封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
电源:3.3 V认证状态:Not Qualified
最大待机电流:0.005 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.16 mA
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

K6R1008V1B-TI8T 数据手册

 浏览型号K6R1008V1B-TI8T的Datasheet PDF文件第3页浏览型号K6R1008V1B-TI8T的Datasheet PDF文件第4页浏览型号K6R1008V1B-TI8T的Datasheet PDF文件第5页浏览型号K6R1008V1B-TI8T的Datasheet PDF文件第7页浏览型号K6R1008V1B-TI8T的Datasheet PDF文件第8页浏览型号K6R1008V1B-TI8T的Datasheet PDF文件第9页 
Preliminary  
PRELIMINARY  
CMOS SRAM  
K6R1008V1B-C/B-L, K6R1008V1B-I/B-P  
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)  
tRC  
Address  
tAA  
tHZ(3,4,5)  
tCO  
CS  
tOE  
tOHZ  
OE  
tOLZ  
tOH  
tLZ(4,5)  
Data out  
Valid Data  
tPU  
tPD  
ICC  
VCC  
50%  
50%  
ISB  
Current  
NOTES(READ CYCLE)  
1. WE is high for read cycle.  
2. All read cycle timing is referenced from the last valid address to the first transition address.  
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or  
VOL levels.  
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to  
device.  
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.  
6. Device is continuously selected with CS=VIL.  
7. Address valid prior to coincident with CS transition low.  
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write  
cycle.  
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)  
tWC  
Address  
OE  
tWR(5)  
tAW  
tCW(3)  
CS  
tWP(2)  
tAS(4)  
WE  
tDW  
tDH  
High-Z  
Data in  
Valid Data  
tOHZ(6)  
High-Z(8)  
Data out  
Rev 2.1  
August 1998  
- 6 -  

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