K4S640832D
CMOS SDRAM
2M x 8Bit x 4 Banks Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
The K4S640832D is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits,
fabricated with SAMSUNG¢s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock
• Burst read single-bit write operation
• DQM for masking
ORDERING INFORMATION
• Auto & self refresh
Part No.
Max Freq.
Interface Package
• 64ms refresh period (4K Cycle)
K4S640832D-TC/L75 133MHz(CL=3)
K4S640832D-TC/L80 125MHz(CL=3)
K4S640832D-TC/L1H 100MHz(CL=2)
K4S640832D-TC/L1L 100MHz(CL=3)
K4S640832D-TC/L10 66MHz(CL=2 &3)
54
LVTTL
TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
LWE
Data Input Register
LDQM
Bank Select
2M x 8
2M x 8
2M x 8
2M x 8
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LRAS
LCBR
LWE
LCAS
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
Samsung Electronics reserves the right to change products or specification without notice.
*
Rev. 0.0 May 1999