K4S640832D
CMOS SDRAM
AC OPERATING TEST CONDITIONS(VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
Input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
3.3V
Vtt = 1.4V
1200W
50W
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Output
Z0 = 50W
50pF
50pF
870W
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
- 1H
20
Parameter
Symbol
Unit
Note
- 75
15
- 80
16
- 1L
20
-10
20
24
24
50
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP(min)
ns
ns
1
1
1
1
20
20
20
20
Row precharge time
20
20
20
20
ns
tRAS(min)
tRAS(max)
tRC(min)
45
48
50
50
ns
Row active time
100
70
us
Row cycle time
65
68
70
80
ns
1
2,5
5
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
2
CLK
-
2 CLK + 20 ns
1
1
1
2
CLK
CLK
CLK
2
2
Col. address to col. address delay
3
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
-
1
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -80/1H/1L/10, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
SAMSUNG recommands tRDL=2CLK and tDAL=2CLK + 20ns.
Rev. 0.0 May 1999