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K3P4C1000E-DC120 PDF预览

K3P4C1000E-DC120

更新时间: 2024-11-25 19:23:39
品牌 Logo 应用领域
三星 - SAMSUNG 有原始数据的样本ROM光电二极管内存集成电路
页数 文件大小 规格书
4页 38K
描述
MASK ROM, 512KX16, 120ns, CMOS, PDIP42, 0.600 INCH, DIP-42

K3P4C1000E-DC120 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP,
针数:42Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.92最长访问时间:120 ns
备用内存宽度:8JESD-30 代码:R-PDIP-T42
长度:52.43 mm内存密度:8388608 bit
内存集成电路类型:MASK ROM内存宽度:16
功能数量:1端子数量:42
字数:524288 words字数代码:512000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512KX16
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:5.08 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:15.24 mmBase Number Matches:1

K3P4C1000E-DC120 数据手册

 浏览型号K3P4C1000E-DC120的Datasheet PDF文件第2页浏览型号K3P4C1000E-DC120的Datasheet PDF文件第3页浏览型号K3P4C1000E-DC120的Datasheet PDF文件第4页 
K3P4C1000E-D(G)C  
CMOS MASK ROM  
8M-Bit (1Mx8 / 512Kx16) CMOS MASK ROM  
FEATURES  
GENERAL DESCRIPTION  
· Switchable organization  
1,048,576 x 8(byte mode)  
524,288 x 16(word mode)  
· Fast access time  
The K3P4C1000E-D(G)C is a fully static mask programmable  
ROM fabricated using silicon gate CMOS process technology,  
and is organized either as 1,048,576 x 8(byte mode) or as  
524,288  
x 16(word mode) depending on BHE voltage  
Random Access : 100ns(Max.)@CL=50pF,  
120ns(Max.)@CL=100pF  
level.(See mode selection table)  
This device includes page read mode function, page read mode  
allows 4 words (or 8 bytes) of data to read fast in the same  
page, CE and A2 ~ A18 should not be changed.  
This device operates with a 5V single power supply, and all  
inputs and outputs are TTL compatible.  
Page Access  
: 30ns(Max.)@CL=50pF  
40ns(Max.)@CL=100pF  
4 Words / 8 Bytes page access  
· Supply voltage : single +5V  
· Current consumption  
Operating : 80mA(Max.)  
Standby : 50mA(Max.)  
Because of its asynchronous operation, it requires no external  
clock assuring extremely easy operation.  
· Fully static operation  
· All inputs and outputs TTL compatible  
· Three state outputs  
It is suitable for use in program memory of microprocessor, and  
data memory, character generator.  
The K3P4C1000E-DC is packaged in  
K3P4C1000E-GC in a 44-SOP.  
a
42-DIP and the  
· Package  
-. K3P4C1000E-DC : 42-DIP-600  
-. K3P4C1000E-GC : 44-SOP-600  
FUNCTIONAL BLOCK DIAGRAM  
PIN CONFIGURATION  
A18  
X
MEMORY CELL  
MATRIX  
(524,288x16/  
1,048,576x8)  
BUFFERS  
AND  
DECODER  
.
.
.
.
.
.
.
.
A18  
1
2
42N.C  
41 A8  
40 A9  
39 A10  
38 A11  
N.C  
A18  
A17  
A7  
N.C  
44  
1
2
A17  
A7  
43 N.C  
3
A8  
42  
3
4
A6  
A5  
4
41 A9  
5
A6  
5
40 A10  
39 A11  
38 A12  
37 A13  
Y
SENSE AMP.  
DATA OUT  
BUFFERS  
6
A4  
A3  
37  
36  
A12  
A13  
A5  
6
BUFFERS  
AND  
DECODER  
7
A4  
7
8
A2  
A1  
35 A14  
34 A15  
33 A16  
32 BHE  
A3  
8
A2  
9
A14  
A15  
A16  
A2  
A1  
9
36  
35  
34  
33  
10  
11  
12  
13  
14  
15  
16  
A0  
CE  
VSS  
OE  
Q0  
10  
11  
A0~A1  
A-1  
. . .  
A0  
DIP  
31  
VSS  
SOP  
CE 12  
BHE  
30  
Q15/A-1  
CE  
VSS  
13  
32 VSS  
29 Q7  
28  
Q0/Q8  
Q7/Q15  
CONTROL  
LOGIC  
OE 14  
Q0 15  
31 Q15/A-1  
OE  
Q8  
Q14  
27 Q6  
Q7  
30  
Q1  
BHE  
Q8  
Q1  
Q9  
16  
17  
18  
29 Q14  
28 Q6  
27 Q13  
26 Q5  
25 Q12  
24 Q4  
23 VCC  
Q9 17  
26  
25  
24  
Q13  
Q5  
18  
Q2  
19  
20  
21  
Q10  
Q3  
Pin Name  
A0 - A1  
Pin Function  
Page Address Inputs  
Q12  
Q2 19  
Q10 20  
Q3 21  
23 Q4  
22  
Q11  
VCC  
A2 - A18  
Q0 - Q14  
Address Inputs  
Q11  
22  
Data Outputs  
K3P4C1000E-DC  
Output 15(Word mode)/  
Q15 /A-1  
LSB Address(Byte mode)  
Word/Byte selection  
Chip Enable  
K3P4C1000E-GC  
BHE  
CE  
OE  
Output Enable  
Power ( +5V)  
Ground  
VCC  
VSS  
N.C  
No Connection  

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