Datasheet > IZ74LV74

IZ74LV74

更新时间： 2024-09-14 23:15:07

品牌	Logo	应用领域
INTEGRAL		/
页数	文件大小	规格书
7页	164K
描述
Dual D-type flip-flop with set and reset; positive-edge trigger

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IZ74LV74 数据手册

TECHNICAL DATA

IN74LV74

Dual D-type flip-flop with set and reset;

positive-edge trigger

N SUFFIX

PLASTIC

The IN74LV74 is a low-voltage Si-gate CMOS device and is pin and

function compatible with 74HC/HCT74.

The IN74LV74 is a dual positive edge triggered, D-type flip-flop with

individual data (D) inputs, clock (CP) inputs, set (S_D) and (R_D) inputs;

also complementary Q and Q outputs.

D SUFFIX

The set and reset are asynchronous active LOW inputs and operate

independently of the clock input. Information on the data input is

transferred to the Q output on the LOW-to-HIGH transition of the clock

pulse. The D inputs must be stable one set-up time prior to the LOW-to-

HIGH clock transition, for predictable operation. Schmitt-trigger action in

the clock input makes the circuit highly tolerant to slower clock rise and

fall times.

SOIC

ORDERING INFORMATION

IN74LV74N

IN74LV74D

IZ74LV74

Plastic DIP

SOIC

chip

Output voltage levels are compatible with input levels of CMOS,

NMOS and TTL IC_S

T_A= -40° to 125° C for all packages

Supply voltage range: 1.2 to 3.6 V

Low input current: 1.0 mÀ; 0.1 mÀ at Ò = 25 °Ñ

High Noise Immunity Characteristic of CMOS Devices

PIN ASSIGNMENT

RESET 1

DATA 1

CLOCK 1

SET 1

13 RESET 2

12 DATA2

11 CLOCK 2

10 SET 2

LOGIC DIAGRAM

GND

FUNCTION TABLE

Inputs

Clock

Outputs

Set

Reset

Data

No Change

PIN 20=V_CC

PIN 10 = GND

*Both outputs will remain high as long as Set and

Reset are low, but the output states are unpredictable

if Set and Reset go high simultaneously.

H= high level

X = don’t care

L = low level

Z = high impedance

INTEGRAL

12 3 4 5 6 7

中文翻译

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