Datasheet > ISPLSI2064VL-165LT44

ISPLSI2064VL-165LT44

更新时间： 2024-10-27 22:16:59

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
14页	188K
描述
2.5V In-System Programmable SuperFAST⑩ High Density PLD

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ISPLSI2064VL-165LT44 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	TQFP-44
针数：	44	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.83	其他特性：	YES
最大时钟频率：	118 MHz	系统内可编程：	YES
JESD-30 代码：	S-PQFP-G44	JESD-609代码：	e0
JTAG BST：	YES	长度：	10 mm
湿度敏感等级：	3	专用输入次数：
I/O 线路数量：	32	宏单元数：	64
端子数量：	44	最高工作温度：	70 °C
最低工作温度：		组织：	0 DEDICATED INPUTS, 32 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP44,.47SQ,32
封装形状：	SQUARE	封装形式：	FLATPACK
峰值回流温度（摄氏度）：	240	电源：	2.5 V
可编程逻辑类型：	EE PLD	传播延迟：	8 ns
认证状态：	Not Qualified	子类别：	Programmable Logic Devices
最大供电电压：	2.7 V	最小供电电压：	2.3 V
标称供电电压：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	10 mm
Base Number Matches：	1

ISPLSI2064VL-165LT44 数据手册

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ispLSI 2064VL

2.5V In-System Programmable

SuperFAST™ High Density PLD

Features

Functional Block Diagram

• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC

Input Bus

— 2000 PLD Gates

Output Routing Pool (ORP)

— 64 and 32 I/O Pin Versions, Four Dedicated Inputs

— 64 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100% Functional, JEDEC and Pinout Compatible with

ispLSI 2064V and 2064VE Devices

Global Routing Pool

(GRP)

• 2.5V LOW VOLTAGE 2064 ARCHITECTURE

Logic

Array

GLB

— Interfaces with Standard 3.3V TTL Devices (Inputs

and I/Os are 3.3V Tolerant)

— 60 mA Typical Active Current

• HIGH-PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 165MHz Maximum Operating Frequency

— tpd = 5.5ns Propagation Delay

Output Routing Pool (ORP)

Input Bus

— Electrically Erasable and Reprogrammable

— Non-Volatile

0139A/2064VL

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

Description

• IN-SYSTEM PROGRAMMABLE

The ispLSI 2064VL is a High Density Programmable

Logic Device available in 64 and 32 I/O-pin versions. The

device contains 64 Registers, four Dedicated Input pins,

three Dedicated Clock Input pins, two dedicated Global

OE input pins and a Global Routing Pool (GRP). The

GRP provides complete interconnectivity between all of

these elements. The ispLSI 2064VL features in-system

programmability through the Boundary Scan Test Ac-

cess Port (TAP) and is 100% IEEE 1149.1 Boundary

Scan Testable. The ispLSI 2064VL offers non-volatile

reprogrammability of the logic, as well as the intercon-

nect, to provide truly reconfigurable systems.

— 2.5V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of Wired-OR

or Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

The basic unit of logic on the ispLSI 2064VL device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1…B7(seeFigure1). Thereareatotalof16GLBsinthe

ispLSI 2064VL device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/ExclusiveORarray, andfouroutputswhichcan

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

September 2000

2064vl_02

12 3 4 5 6 7...14

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与ISPLSI2064VL-165LT44相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI2096-100LQ	ROCHESTER	获取价格	EE PLD, 13 ns, PQFP128, PLASTIC, QFP-128
ISPLSI2096-125LQ	ROCHESTER	获取价格	EE PLD, 10 ns, PQFP128, PLASTIC, QFP-128
ISPLSI2096-80LQ	ROCHESTER	获取价格	EE PLD, 18.5 ns, PQFP128, PLASTIC, QFP-128
ISPLSI2096-80LQI	LATTICE	获取价格	EE PLD, 18.5ns, 96-Cell, CMOS, PQFP128, PLASTIC, QFP-128
ISPLSI2096-80LQI	ROCHESTER	获取价格	EE PLD, 18.5 ns, PQFP128, PLASTIC, QFP-128
ISPLSI2096-80LTI	LATTICE	获取价格	EE PLD, 18.5ns, 96-Cell, CMOS, PQFP128, TQFP-128
ISPLSI2096A-100LQ128	ETC	获取价格
ISPLSI2096A-100LT128	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI2096A-125LQ128	LATTICE	获取价格	EE PLD, 10ns, 96-Cell, CMOS, PQFP128, PLASTIC, QFP-128
ISPLSI2096A-125LT128	LATTICE	获取价格	EE PLD, 10ns, 96-Cell, CMOS, PQFP128, TQFP-128

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