Datasheet > ISPLSI2096A-100LQ128

ISPLSI2096A-100LQ128

更新时间： 2024-10-27 23:59:51

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ISPLSI2096A-100LQ128 数据手册

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ispLSI 2096/A

In-System Programmable High Density PLD

Features

Functional Block Diagram

• ENHANCEMENTS

— ispLSI 2096A is Fully Form and Function Compatible

to the ispLSI 2096, with Identical Timing

Specifcations and Packaging

Output Routing Pool (ORP)

C3 C2 C1 C0

— ispLSI 2096A is Built on an Advanced 0.35 Micron

E²CMOS^®Technology

Logic

Array

• HIGH DENSITY PROGRAMMABLE LOGIC

Global Routing Pool

(GRP)

GLB

— 4000 PLD Gates

— 96 I/O Pins, Six Dedicated Inputs

— 96 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

Output Routing Pool (ORP)

0919/2096

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

Description

— fmax = 125 MHz Maximum Operating Frequency

— tpd = 7.5 ns Propagation Delay

The ispLSI 2096 and 2096A are High Density Program-

mable Logic Devices. The devices contain 96 Registers,

96 Universal I/O pins, six Dedicated Input pins, three

Dedicated Clock Input pins, two dedicated Global OE

input pins and a Global Routing Pool (GRP). The GRP

provides complete interconnectivity between all of these

elements. The ispLSI 2096 and 2096A feature 5V in-

system programmability and in-system diagnostic

capabilities. The ispLSI 2096 and 2096A offer non-

volatile reprogrammability of the logic, as well as the

interconnect to provide truly reconfigurable systems.

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— In-System Programmable (ISP™) 5V Only

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

The basic unit of logic on these devices is the Generic

Logic Block (GLB). The GLBs are labeled A0, A1…C7

(Figure1). Thereareatotalof24GLBsintheispLSI2096

and 2096A devices. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/ExclusiveORarray, andfouroutputswhichcan

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

— Complete Programmable Device Can Combine

Glue Logic and Structured Designs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

January 2002

2096_08

12 3 4 5 6 7...11

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与ISPLSI2096A-100LQ128相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI2096A-100LT128	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI2096A-125LQ128	LATTICE	获取价格	EE PLD, 10ns, 96-Cell, CMOS, PQFP128, PLASTIC, QFP-128
ISPLSI2096A-125LT128	LATTICE	获取价格	EE PLD, 10ns, 96-Cell, CMOS, PQFP128, TQFP-128
ISPLSI2096A-80LQ128	LATTICE	获取价格	EE PLD, 18.5ns, 96-Cell, CMOS, PQFP128, PLASTIC, QFP-128
ISPLSI2096A-80LQ128I	LATTICE	获取价格	EE PLD, 18.5ns, 96-Cell, CMOS, PQFP128, PLASTIC, QFP-128
ISPLSI2096A-80LT128	ETC	获取价格
ISPLSI2096A-80LT128I	LATTICE	获取价格	EE PLD, 18.5ns, 96-Cell, CMOS, PQFP128, TQFP-128
ISPLSI2096A-80LTN128	LATTICE	获取价格	EE PLD, 18.5ns, 96-Cell, CMOS, PQFP128, LEAD FREE, TQFP-128
ISPLSI2096A-80LTN128I	LATTICE	获取价格	EE PLD, 18.5ns, 96-Cell, CMOS, PQFP128, LEAD FREE, TQFP-128
ISPLSI2096E-100LQ128	LATTICE	获取价格	In-System Programmable SuperFAST⑩ High Densit

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