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ISPLSI2096E-135LQ128 PDF预览

ISPLSI2096E-135LQ128

更新时间： 2024-10-27 22:18:27
品牌 Logo 应用领域
莱迪思 - LATTICE /
页数 文件大小 规格书
11页 144K
描述
In-System Programmable SuperFAST⑩ High Density PLD

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中文翻译

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ISPLSI2096E-135LQ128 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：PLASTIC, QFP-128针数：128
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.79
其他特性：CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V最大时钟频率：100 MHz
系统内可编程：YESJESD-30 代码：S-PQFP-G128
JESD-609代码：e0JTAG BST：NO
长度：28 mm湿度敏感等级：3
专用输入次数：3I/O 线路数量：96
宏单元数：96端子数量：128
最高工作温度：70 °C最低工作温度：
组织：3 DEDICATED INPUTS, 96 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP128,1.2SQ,32封装形状：SQUARE
封装形式：FLATPACK峰值回流温度（摄氏度）：225
电源：3.3/5,5 V可编程逻辑类型：EE PLD
传播延迟：7.5 ns认证状态：Not Qualified
座面最大高度：4.1 mm子类别：Programmable Logic Devices
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：28 mm
Base Number Matches：1

ISPLSI2096E-135LQ128 数据手册

 浏览型号ISPLSI2096E-135LQ128的Datasheet PDF文件第2页浏览型号ISPLSI2096E-135LQ128的Datasheet PDF文件第3页浏览型号ISPLSI2096E-135LQ128的Datasheet PDF文件第4页浏览型号ISPLSI2096E-135LQ128的Datasheet PDF文件第5页浏览型号ISPLSI2096E-135LQ128的Datasheet PDF文件第6页浏览型号ISPLSI2096E-135LQ128的Datasheet PDF文件第7页 
®
ispLSI 2096E  
In-System Programmable  
SuperFAST™ High Density PLD  
Features  
Functional Block Diagram  
• SUPERFAST HIGH DENSITY IN-SYSTEM  
PROGRAMMABLE LOGIC  
Output Routing Pool (ORP)  
Output Routing Pool (ORP)  
C3 C2 C1 C0  
C7  
C6  
C5  
C4  
— 4000 PLD Gates  
— 96 I/O Pins, Six Dedicated Inputs  
— 96 Registers  
A0  
A1  
A2  
A3  
B7  
B6  
B5  
B4  
D
D
D
D
Q
Q
Q
Q
— High Speed Global Interconnect  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
— Small Logic Block Size for Random Logic  
— 100% Functional/JEDEC Upward Compatible with  
ispLSI 2096 Devices  
Logic  
Array  
Global Routing Pool  
(GRP)  
GLB  
A4  
A5  
A6  
A7  
B0  
B1  
B2  
B3  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
Output Routing Pool (ORP)  
Output Routing Pool (ORP)  
— fmax = 180 MHz Maximum Operating Frequency  
— tpd = 5.0 ns Propagation Delay  
— TTL Compatible Inputs and Outputs  
— 5V Programmable Logic Core  
0919/2096E  
Description  
— ispJTAG™ In-System Programmable via IEEE 1149.1  
(JTAG) Test Access Port  
— User-Selectable 3.3V or 5V I/O Supports Mixed-  
Voltage Systems  
— PCI Compatible Outputs  
— Open-Drain Output Option  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
— Unused Product Term Shutdown Saves Power  
The ispLSI 2096E is a High Density Programmable Logic  
Device. The device contains 96 Registers, 96 Universal  
I/O pins, six Dedicated Input pins, three Dedicated Clock  
Input pins, two dedicated Global OE input pins and a  
GlobalRouting Pool(GRP). TheGRPprovidescomplete  
interconnectivity between all of these elements. The  
ispLSI 2096E features 5V in-system programmability  
and in-system diagnostic capabilities. The ispLSI 2096E  
offers non-volatile reprogrammability of all logic, as well  
as the interconnect to provide truly reconfigurable sys-  
tems.  
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES  
— Increased Manufacturing Yields, Reduced Time-to-  
Market and Improved Product Quality  
— Reprogram Soldered Devices for Faster Prototyping  
The basic unit of logic on the ispLSI 2096E device is the  
Generic Logic Block (GLB). The GLBs are labeled A0, A1  
.. C7 (see Figure 1). There are a total of 24 GLBs in the  
ispLSI 2096E device. Each GLB is made up of four  
macrocells. Each GLB has 18 inputs, a programmable  
AND/OR/ExclusiveORarray, andfouroutputswhichcan  
be configured to be either combinatorial or  
registered.Inputs to the GLB come from the GRP and  
dedicated inputs. All of the GLB outputs are brought back  
into the GRP so that they can be connected to the inputs  
of any GLB on the device.  
• OFFERS THE EASE OF USE AND FAST SYSTEM  
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY  
OF FIELD PROGRAMMABLE GATE ARRAYS  
— Complete Programmable Device Can Combine Glue  
Logic and Structured Designs  
— Enhanced Pin Locking Capability  
— Three Dedicated Clock Input Pins  
— Synchronous and Asynchronous Clocks  
— Programmable Output Slew Rate Control to  
Minimize Switching Noise  
— Flexible Pin Placement  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
The device also has 96 I/O cells, each of which is directly  
connected to an I/O pin. Each I/O cell can be individually  
programmed to be a combinatorial input, output or bi-  
directional I/O pin with 3-state control. The signal levels  
are TTL compatible voltages and the output drivers can  
source 4 mA or sink 8 mA. Each output can be pro-  
grammed independently for fast or slow output slew rate  
tominimizeoveralloutputswitchingnoise. Byconnecting  
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-  
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL  
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING  
— Superior Quality of Results  
— Tightly Integrated with Leading CAE Vendor Tools  
— Productivity Enhancing Timing Analyzer, Explore  
Tools, Timing Simulator and ispANALYZER™  
— PC and UNIX Platforms  
Copyright©1998LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
November 1998  
2096e_03  
1
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中文翻译

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ISPLSI2096E-135LQ128 替代型号

型号 品牌 替代类型 描述 数据表
ISPLSI2096E-100LQ128 LATTICE

完全替代

 In-System Programmable SuperFAST⑩ High Densit
ISPLSI2096A-80LQ128 LATTICE

类似代替

 EE PLD, 18.5ns, 96-Cell, CMOS, PQFP128, PLASTIC, QFP-128
ISPLSI2096A-125LQ128 LATTICE

类似代替

 EE PLD, 10ns, 96-Cell, CMOS, PQFP128, PLASTIC, QFP-128

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ISPLSI2096E-180LQ128 LATTICE

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 		In-System Programmable SuperFAST⑩ High Densit
ISPLSI2096E-180LT128 LATTICE

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 		In-System Programmable SuperFAST⑩ High Densit
ISPLSI2096V-60LQ128 ETC

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 		Electrically-Erasable Complex PLD
ISPLSI2096V-60LQI LATTICE

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 		EE PLD, 20ns, CMOS, PQFP128, PLASTIC, QFP-128
ISPLSI2096V-60LT LATTICE

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 		EE PLD, 20ns, CMOS, PQFP128, TQFP-128
ISPLSI2096V-60LT128 LATTICE

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 		EE PLD, 20ns, 96-Cell, CMOS, PQFP128, TQFP-128
ISPLSI2096V-60LT128I ETC

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 		Electrically-Erasable Complex PLD
ISPLSI2096V-60LTI LATTICE

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 		EE PLD, 20ns, CMOS, PQFP128, PLASTIC, QFP-128
ISPLSI2096V-80LQ LATTICE

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