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ISPLSI2096VE-200LT128 PDF预览

ISPLSI2096VE-200LT128

更新时间： 2024-11-17 22:21:27
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
12页 161K
描述
3.3V In-System Programmable SuperFAST⑩ High Density PLD

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ISPLSI2096VE-200LT128 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：TQFP-128
针数：128Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.74其他特性：USE ISPLSI 2096VE-250 FOR NEW DESIGNS
最大时钟频率：133 MHz系统内可编程：YES
JESD-30 代码：S-PQFP-G128JESD-609代码：e0
JTAG BST：NO长度：14 mm
湿度敏感等级：3专用输入次数：2
I/O 线路数量：96宏单元数：96
端子数量：128最高工作温度：70 °C
最低工作温度：组织：2 DEDICATED INPUTS, 96 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP128,.64SQ,16
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
电源：3.3 V可编程逻辑类型：EE PLD
传播延迟：7 ns认证状态：Not Qualified
座面最大高度：1.6 mm子类别：Programmable Logic Devices
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.4 mm端子位置：QUAD
宽度：14 mmBase Number Matches：1

ISPLSI2096VE-200LT128 数据手册

 浏览型号ISPLSI2096VE-200LT128的Datasheet PDF文件第2页浏览型号ISPLSI2096VE-200LT128的Datasheet PDF文件第3页浏览型号ISPLSI2096VE-200LT128的Datasheet PDF文件第4页浏览型号ISPLSI2096VE-200LT128的Datasheet PDF文件第5页浏览型号ISPLSI2096VE-200LT128的Datasheet PDF文件第6页浏览型号ISPLSI2096VE-200LT128的Datasheet PDF文件第7页 
®
ispLSI 2096VE  
3.3V In-System Programmable  
SuperFAST™ High Density PLD  
Features  
Functional Block Diagram  
• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC  
— 4000 PLD Gates  
— 96 I/O Pins, Six Dedicated Inputs  
— 96 Registers  
Output Routing Pool (ORP)  
Output Routing Pool (ORP)  
C3 C2 C1 C0  
C7  
C6  
C5  
C4  
— High Speed Global Interconnect  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
— Small Logic Block Size for Random Logic  
— 100% Functional, JEDEC and Pinout Compatible  
with ispLSI 2096V Devices  
A0  
A1  
A2  
A3  
B7  
B6  
B5  
B4  
D
D
D
D
Q
Q
Q
Q
Logic  
Array  
Global Routing Pool  
(GRP)  
GLB  
— Pinout Compatible with ispLSI 2192VE  
A4  
A5  
A6  
A7  
B0  
B1  
B2  
B3  
• 3.3V LOW VOLTAGE 2096 ARCHITECTURE  
— Interfaces with Standard 5V TTL Devices  
Output Routing Pool (ORP)  
Output Routing Pool (ORP)  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— fmax = 250MHz* Maximum Operating Frequency  
— tpd = 4.0ns* Propagation Delay  
0919/2096VE  
Description  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
The ispLSI 2096VE is a High Density Programmable  
Logic Device containing 96 Registers, six Dedicated  
Input pins, three Dedicated Clock Input pins, two dedi-  
cated Global OE input pins and a Global Routing Pool  
(GRP). The GRP provides complete interconnectivity  
between all of these elements. The ispLSI 2096VE  
features in-system programmability through the Bound-  
ary Scan Test Access Port (TAP) and is 100% IEEE  
1149.1 Boundary Scan Testable. The ispLSI 2096VE  
offers non-volatile reprogrammability of the logic, as well  
as the interconnect to provide truly reconfigurable sys-  
tems.  
— 100% Tested at Time of Manufacture  
— Unused Product Term Shutdown Saves Power  
• IN-SYSTEM PROGRAMMABLE  
— 3.3V In-System Programmability (ISP™) Using  
Boundary Scan Test Access Port (TAP)  
— Open-Drain Output Option for Flexible Bus Interface  
Capability, Allowing Easy Implementation of  
Wired-OR or Bus Arbitration Logic  
— Increased Manufacturing Yields, Reduced Time-to-  
Market and Improved Product Quality  
— Reprogram Soldered Devices for Faster Prototyping  
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE  
The basic unit of logic on the ispLSI 2096VE device is the  
Generic Logic Block (GLB). The GLBs are labeled A0, A1  
.. C7 (see Figure 1). There are a total of 24 GLBs in the  
ispLSI 2096VE device. Each GLB is made up of four  
macrocells. Each GLB has 18 inputs, a programmable  
AND/OR/ExclusiveORarray, andfouroutputswhichcan  
be configured to be either combinatorial or registered.  
Inputs to the GLB come from the GRP and dedicated  
inputs. All of the GLB outputs are brought back into the  
GRP so that they can be connected to the inputs of any  
GLB on the device.  
• THE EASE OF USE AND FAST SYSTEM SPEED OF  
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS  
— Enhanced Pin Locking Capability  
— Three Dedicated Clock Input Pins  
— Synchronous and Asynchronous Clocks  
— Programmable Output Slew Rate Control  
— Flexible Pin Placement  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-  
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL  
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING  
— Superior Quality of Results  
— Tightly Integrated with Leading CAE Vendor Tools  
— Productivity Enhancing Timing Analyzer, Explore  
Tools, Timing Simulator and ispANALYZER™  
— PC and UNIX Platforms  
The devices also have 96 I/O cells, each of which is  
directly connected to an I/O pin. Each I/O cell can be  
individually programmed to be a combinatorial input,  
output or bi-directional I/O pin with 3-state control. The  
signal levels are TTL compatible voltages and the output  
drivers can source 4 mA or sink 8 mA. Each output can  
*Advanced Information  
Copyright©2000LatticeSemiconductorCorp.Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
September 2000  
2096ve_05  
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