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ISPLSI2096VE-100LTN128 PDF预览

ISPLSI2096VE-100LTN128

更新时间： 2024-10-28 14:42:55
品牌 Logo 应用领域
莱迪思 - LATTICE 时钟输入元件可编程逻辑
页数 文件大小 规格书
13页 139K
描述
EE PLD, 13ns, 96-Cell, CMOS, PQFP128, LEAD FREE, TQFP-128

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ISPLSI2096VE-100LTN128 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LFQFP, QFP128,.64SQ,16针数：128
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.7
Is Samacsys：N其他特性：YES
最大时钟频率：77 MHz系统内可编程：YES
JESD-30 代码：S-PQFP-G128JESD-609代码：e3
JTAG BST：NO长度：14 mm
湿度敏感等级：3专用输入次数：2
I/O 线路数量：96宏单元数：96
端子数量：128最高工作温度：70 °C
最低工作温度：组织：2 DEDICATED INPUTS, 96 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP128,.64SQ,16
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
可编程逻辑类型：EE PLD传播延迟：13 ns
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Programmable Logic Devices最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.4 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：14 mmBase Number Matches：1

ISPLSI2096VE-100LTN128 数据手册

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®
Lead-  
ee  
ispLSI 2096VE  
Fr  
Packag  
Options  
ailable!  
e
3.3V In-System Programmable  
SuperFAST™ High Density PLD  
Av  
Features  
Functional Block Diagram  
• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC  
— 4000 PLD Gates  
— 96 I/O Pins, Six Dedicated Inputs  
— 96 Registers  
Output Routing Pool (ORP)  
Output Routing Pool (ORP)  
C3 C2 C1 C0  
C7  
C6  
C5  
C4  
— High Speed Global Interconnect  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
— Small Logic Block Size for Random Logic  
— 100% Functional, JEDEC and Pinout Compatible  
with ispLSI 2096V Devices  
A0  
A1  
A2  
A3  
B7  
B6  
B5  
B4  
D
D
D
D
Q
Q
Q
Q
Logic  
Array  
Global Routing Pool  
(GRP)  
GLB  
— Pinout Compatible with ispLSI 2192VE  
A4  
A5  
A6  
A7  
B0  
B1  
B2  
B3  
• 3.3V LOW VOLTAGE 2096 ARCHITECTURE  
— Interfaces with Standard 5V TTL Devices  
Output Routing Pool (ORP)  
Output Routing Pool (ORP)  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— fmax = 250MHz Maximum Operating Frequency  
— tpd = 4.0ns Propagation Delay  
0919/2096VE  
Description  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
The ispLSI 2096VE is a High Density Programmable  
Logic Device containing 96 Registers, six Dedicated  
Input pins, three Dedicated Clock Input pins, two dedi-  
cated Global OE input pins and a Global Routing Pool  
(GRP). The GRP provides complete interconnectivity  
between all of these elements. The ispLSI 2096VE  
features in-system programmability through the Bound-  
ary Scan Test Access Port (TAP) and is 100% IEEE  
1149.1 Boundary Scan Testable. The ispLSI 2096VE  
offers non-volatile reprogrammability of the logic, as well  
as the interconnect to provide truly reconfigurable sys-  
tems.  
— 100% Tested at Time of Manufacture  
— Unused Product Term Shutdown Saves Power  
• IN-SYSTEM PROGRAMMABLE  
— 3.3V In-System Programmability (ISP™) Using  
Boundary Scan Test Access Port (TAP)  
— Open-Drain Output Option for Flexible Bus Interface  
Capability, Allowing Easy Implementation of  
Wired-OR or Bus Arbitration Logic  
— Increased Manufacturing Yields, Reduced Time-to-  
Market and Improved Product Quality  
— Reprogram Soldered Devices for Faster Prototyping  
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE  
The basic unit of logic on the ispLSI 2096VE device is the  
Generic Logic Block (GLB). The GLBs are labeled A0, A1  
.. C7 (see Figure 1). There are a total of 24 GLBs in the  
ispLSI 2096VE device. Each GLB is made up of four  
macrocells. Each GLB has 18 inputs, a programmable  
AND/OR/ExclusiveORarray, andfouroutputswhichcan  
be configured to be either combinatorial or registered.  
Inputs to the GLB come from the GRP and dedicated  
inputs. All of the GLB outputs are brought back into the  
GRP so that they can be connected to the inputs of any  
GLB on the device.  
• THE EASE OF USE AND FAST SYSTEM SPEED OF  
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS  
— Enhanced Pin Locking Capability  
— Three Dedicated Clock Input Pins  
— Synchronous and Asynchronous Clocks  
— Programmable Output Slew Rate Control  
— Flexible Pin Placement  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
• LEAD-FREE PACKAGE OPTIONS  
The devices also have 96 I/O cells, each of which is  
directly connected to an I/O pin. Each I/O cell can be  
individually programmed to be a combinatorial input,  
output or bi-directional I/O pin with 3-state control. The  
signal levels are TTL compatible voltages and the output  
drivers can source 4 mA or sink 8 mA. Each output can  
Copyright©2004LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
August 2004  
2096ve_08  
1
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中文翻译

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ISPLSI2096VE-100LTN128 替代型号

型号 品牌 替代类型 描述 数据表
ISPLSI2096VE-100LT128 LATTICE

完全替代

 3.3V In-System Programmable SuperFAST⑩ High D

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