Datasheet > ISPLSI2096V-60LT128I

ISPLSI2096V-60LT128I

更新时间： 2024-10-27 23:59:51

品牌	Logo	应用领域
其他 - ETC		可编程逻辑器件输入元件时钟
页数	文件大小	规格书
11页	144K
描述
Electrically-Erasable Complex PLD

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ispLSI 2096V

3.3V High Density Programmable Logic

Features

Functional Block Diagram

• HIGH DENSITY PROGRAMMABLE LOGIC

— 4000 PLD Gates

— 96 I/O Pins, Six Dedicated Inputs

— 96 Registers

Output Routing Pool (ORP)

C3 C2 C1 C0

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

Logic

Array

Global Routing Pool

(GRP)

GLB

• 3.3V LOW VOLTAGE 2096 ARCHITECTURE

— Interfaces with Standard 5V TTL Devices

— Fuse Map Compatible with 5V ispLSI 2096

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

Output Routing Pool (ORP)

— fmax = 80 MHz Maximum Operating Frequency

— tpd = 10 ns Propagation Delay

0919/2096V

— Electrically Erasable and Reprogrammable

— Non-Volatile

Description

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

The ispLSI 2096V is a High Density Programmable Logic

Devicecontaining96Registers, sixDedicatedInputpins,

three Dedicated Clock Input pins, two dedicated Global

OE input pins and a Global Routing Pool (GRP). The

GRP provides complete interconnectivity between all of

these elements. The ispLSI 2096V features in-system

programmability through the Boundary Scan Test Ac-

cess Port (TAP). The ispLSI 2096V offers non-volatile

reprogrammability of the logic, as well as the intercon-

nect to provide truly reconfigurable systems.

• IN-SYSTEM PROGRAMMABLE

— 3.3V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of

Wired-OR or Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS

The basic unit of logic on the ispLSI 2096V device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. C7 (see Figure 1). There are a total of 24 GLBs in the

ispLSI 2096V device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/ExclusiveORarray, andfouroutputswhichcan

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

The devices also have 96 I/O cells, each of which is

directly connected to an I/O pin. Each I/O cell can be

individually programmed to be a combinatorial input,

output or bi-directional I/O pin with 3-state control. The

signal levels are TTL compatible voltages and the output

drivers can source 4 mA or sink 8 mA. Each output can

be programmed independently for fast or slow output

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

February 2000

2096v_08

12 3 4 5 6 7...11

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与ISPLSI2096V-60LT128I相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI2096V-60LTI	LATTICE	获取价格	EE PLD, 20ns, CMOS, PQFP128, PLASTIC, QFP-128
ISPLSI2096V-80LQ	LATTICE	获取价格	EE PLD, 15ns, CMOS, PQFP128, PLASTIC, QFP-128
ISPLSI2096V-80LQ128	LATTICE	获取价格	EE PLD, 15ns, 96-Cell, CMOS, PQFP128, PLASTIC, QFP-128
ISPLSI2096V-80LT128	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI2096VE-100LT128	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2096VE-100LT128I	LATTICE	获取价格	EE PLD, 13ns, CMOS, PQFP128, TQFP-128
ISPLSI2096VE-100LTN128	LATTICE	获取价格	EE PLD, 13ns, 96-Cell, CMOS, PQFP128, LEAD FREE, TQFP-128
ISPLSI2096VE-135LQ	LATTICE	获取价格	EE PLD, 5ns, CMOS, PQFP128, PLASTIC, QFP-128
ISPLSI2096VE-135LQ128	LATTICE	获取价格	EE PLD, 10ns, CMOS, PQFP128, PLASTIC, QFP-128
ISPLSI2096VE-135LT	LATTICE	获取价格	EE PLD, 5ns, CMOS, PQFP128, TQFP-128

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