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ISPLSI2096A-125LT128 PDF预览

ISPLSI2096A-125LT128

更新时间： 2024-10-28 20:05:15
品牌 Logo 应用领域
莱迪思 - LATTICE 时钟输入元件可编程逻辑
页数 文件大小 规格书
12页 396K
描述
EE PLD, 10ns, 96-Cell, CMOS, PQFP128, TQFP-128

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ISPLSI2096A-125LT128 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TQFP-128针数：128
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.79
Is Samacsys：N其他特性：YES
最大时钟频率：100 MHz系统内可编程：YES
JESD-30 代码：S-PQFP-G128JESD-609代码：e0
JTAG BST：NO长度：14 mm
湿度敏感等级：3专用输入次数：3
I/O 线路数量：96宏单元数：96
端子数量：128最高工作温度：70 °C
最低工作温度：组织：3 DEDICATED INPUTS, 96 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP128,.64SQ,16
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：240电源：5 V
可编程逻辑类型：EE PLD传播延迟：10 ns
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Programmable Logic Devices最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.4 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

ISPLSI2096A-125LT128 数据手册

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Lead-  
ee  
Fr  
Package  
®
Options  
vailable!  
ispLSI 2096/A  
A
In-System Programmable High Density PLD  
Features  
Functional Block Diagram  
• ENHANCEMENTS  
— ispLSI 2096A is Fully Form and Function Compatible  
to the ispLSI 2096, with Identical Timing  
Specifcations and Packaging  
Output Routing Pool (ORP)  
Output Routing Pool (ORP)  
C3 C2 C1 C0  
C7  
C6  
C5  
C4  
A0  
A1  
A2  
A3  
B7  
B6  
B5  
B4  
— ispLSI 2096A is Built on an Advanced 0.35 Micron  
D
D
D
D
Q
Q
Q
Q
E2CMOS® Technology  
Logic  
Array  
• HIGH DENSITY PROGRAMMABLE LOGIC  
Global Routing Pool  
(GRP)  
GLB  
— 4000 PLD Gates  
— 96 I/O Pins, Six Dedicated Inputs  
— 96 Registers  
— High Speed Global Interconnect  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
— Small Logic Block Size for Random Logic  
A4  
A5  
A6  
A7  
B0  
B1  
B2  
B3  
Output Routing Pool (ORP)  
Output Routing Pool (ORP)  
0919/2096  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
Description  
— fmax = 125 MHz Maximum Operating Frequency  
— tpd = 7.5 ns Propagation Delay  
The ispLSI 2096 and 2096A are High Density Program-  
mable Logic Devices. The devices contain 96 Registers,  
96 Universal I/O pins, six Dedicated Input pins, three  
Dedicated Clock Input pins, two dedicated Global OE  
input pins and a Global Routing Pool (GRP). The GRP  
provides complete interconnectivity between all of these  
elements. The ispLSI 2096 and 2096A feature 5V in-  
system programmability and in-system diagnostic  
capabilities. The ispLSI 2096 and 2096A offer non-  
volatile reprogrammability of the logic, as well as the  
interconnect to provide truly reconfigurable systems.  
— TTL Compatible Inputs and Outputs  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
— 100% Tested at Time of Manufacture  
— Unused Product Term Shutdown Saves Power  
• IN-SYSTEM PROGRAMMABLE  
— In-System Programmable (ISP™) 5V Only  
— Increased Manufacturing Yields, Reduced Time-to-  
Market and Improved Product Quality  
— Reprogram Soldered Devices for Faster Prototyping  
• OFFERS THE EASE OF USE AND FAST SYSTEM  
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY  
OF FIELD PROGRAMMABLE GATE ARRAYS  
The basic unit of logic on these devices is the Generic  
Logic Block (GLB). The GLBs are labeled A0, A1…C7  
(Figure1). Thereareatotalof24GLBsintheispLSI2096  
and 2096A devices. Each GLB is made up of four  
macrocells. Each GLB has 18 inputs, a programmable  
AND/OR/ExclusiveORarray, andfouroutputswhichcan  
be configured to be either combinatorial or registered.  
Inputs to the GLB come from the GRP and dedicated  
inputs. All of the GLB outputs are brought back into the  
GRP so that they can be connected to the inputs of any  
GLB on the device.  
— Complete Programmable Device Can Combine  
Glue Logic and Structured Designs  
— Enhanced Pin Locking Capability  
— Three Dedicated Clock Input Pins  
— Synchronous and Asynchronous Clocks  
— Programmable Output Slew Rate Control to  
Minimize Switching Noise  
— Flexible Pin Placement  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
— Lead-Free Package Options  
Copyright©2006LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
August 2006  
2096_09  
1
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ISPLSI2096A-125LT128 替代型号

型号 品牌 替代类型 描述 数据表
ISPLSI2096-80LTI LATTICE

功能相似

 EE PLD, 18.5ns, 96-Cell, CMOS, PQFP128, TQFP-128

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