Datasheet > ISPLSI2064A-125LT100

ISPLSI2064A-125LT100

更新时间： 2024-10-27 23:59:51

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ispLSI 2064/A

In-System Programmable High Density PLD

Features

Functional Block Diagram

• ENHANCEMENTS

— ispLSI 2064A is Fully Form and Function Compatible

to the ispLSI 2064, with Identical Timing

Specifcations and Packaging

Input Bus

Output Routing Pool (ORP)

— ispLSI 2064A is Built on an Advanced 0.35 Micron

E²CMOS^®Technology

Global Routing Pool

(GRP)

• HIGH DENSITY PROGRAMMABLE LOGIC

— 2000 PLD Gates

— 64 I/O Pins, Four Dedicated Inputs

— 64 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

Logic

Array

GLB

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 125 MHz Maximum Operating Frequency

— tpd = 7.5 ns Propagation Delay

Output Routing Pool (ORP)

Input Bus

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

0139Bisp/2064

Description

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

The ispLSI 2064 and 2064A are High Density Program-

mable Logic Devices. The devices contain 64 Registers,

64 Universal I/O pins, four Dedicated Input pins, three

Dedicated Clock Input pins, two dedicated Global OE

input pins and a Global Routing Pool (GRP). The GRP

provides complete interconnectivity between all of these

elements. The 2064 and 2064A feature 5V in-system

programmability and in-system diagnostic capabilities.

The ispLSI 2064 and 2064A offer non-volatile

reprogrammability of the logic, as well as the intercon-

nect, to provide truly reconfigurable systems.

• IN-SYSTEM PROGRAMMABLE

— In-System Programmable (ISP™) 5V Only

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

The basic unit of logic on these devices is the Generic

Logic Block (GLB). The GLBs are labeled A0, A1…B7

(Figure1). Thereareatotalof16GLBsintheispLSI2064

and 2064A devices. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/ExclusiveORarray, andfouroutputswhichcan

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

January 2002

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

2064_09

12 3 4 5 6 7...13

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与ISPLSI2064A-125LT100相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI2064A-80LJ84	LATTICE	获取价格	EE PLD, 18.5ns, 64-Cell, CMOS, PQCC84, PLASTIC, LCC-84
ISPLSI2064A-80LJ84I	LATTICE	获取价格	EE PLD, 18.5ns, 64-Cell, CMOS, PQCC84, PLASTIC, LCC-84
ISPLSI2064A-80LJN84	LATTICE	获取价格	EE PLD, 18.5ns, 64-Cell, CMOS, PQCC84, LEAD FREE, PLASTIC, LCC-84
ISPLSI2064A-80LT100	LATTICE	获取价格	EE PLD, 18.5ns, 64-Cell, CMOS, PQFP100, TQFP-100
ISPLSI2064A-80LT100I	LATTICE	获取价格	EE PLD, 18.5ns, 64-Cell, CMOS, PQFP100, TQFP-100
ISPLSI2064A-80LTN100	LATTICE	获取价格	EE PLD, 18.5ns, 64-Cell, CMOS, PQFP100, LEAD FREE, TQFP-100
ISPLSI2064E-100LT	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI2064E-100LT100	LATTICE	获取价格	In-System Programmable SuperFAST⑩ High Densit
ISPLSI2064E-135LT	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI2064E-135LT100	LATTICE	获取价格	In-System Programmable SuperFAST⑩ High Densit

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