5秒后页面跳转
捷配首页

Datasheet > ISPLSI2064A-80LJ84
ISPLSI2064A-80LJ84 PDF预览

ISPLSI2064A-80LJ84

更新时间： 2024-10-28 19:06:19
品牌 Logo 应用领域
莱迪思 - LATTICE 时钟输入元件可编程逻辑
页数 文件大小 规格书
14页 417K
描述
EE PLD, 18.5ns, 64-Cell, CMOS, PQCC84, PLASTIC, LCC-84

阅读下载

中文翻译

获取价格

ISPLSI2064A-80LJ84 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：LCC
包装说明：PLASTIC, LCC-84针数：84
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.77
其他特性：YES最大时钟频率：57 MHz
系统内可编程：YESJESD-30 代码：S-PQCC-J84
JESD-609代码：e0JTAG BST：NO
长度：29.3116 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：64
宏单元数：64端子数量：84
最高工作温度：70 °C最低工作温度：
组织：0 DEDICATED INPUTS, 64 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC84,1.2SQ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：225
电源：5 V可编程逻辑类型：EE PLD
传播延迟：18.5 ns认证状态：Not Qualified
座面最大高度：4.572 mm子类别：Programmable Logic Devices
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：29.3116 mm
Base Number Matches：1

ISPLSI2064A-80LJ84 数据手册

 浏览型号ISPLSI2064A-80LJ84的Datasheet PDF文件第2页浏览型号ISPLSI2064A-80LJ84的Datasheet PDF文件第3页浏览型号ISPLSI2064A-80LJ84的Datasheet PDF文件第4页浏览型号ISPLSI2064A-80LJ84的Datasheet PDF文件第5页浏览型号ISPLSI2064A-80LJ84的Datasheet PDF文件第6页浏览型号ISPLSI2064A-80LJ84的Datasheet PDF文件第7页 
Lead-  
ee  
Fr  
®
Package  
ispLSI 2064/A  
Options  
vailable!  
A
In-System Programmable High Density PLD  
Features  
Functional Block Diagram  
• ENHANCEMENTS  
— ispLSI 2064A is Fully Form and Function Compatible  
to the ispLSI 2064, with Identical Timing  
Specifcations and Packaging  
Input Bus  
Output Routing Pool (ORP)  
— ispLSI 2064A is Built on an Advanced 0.35 Micron  
E2CMOS® Technology  
Global Routing Pool  
(GRP)  
• HIGH DENSITY PROGRAMMABLE LOGIC  
A0  
A1  
A2  
A3  
B3  
B2  
B1  
B0  
— 2000 PLD Gates  
— 64 I/O Pins, Four Dedicated Inputs  
— 64 Registers  
— High Speed Global Interconnect  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
— Small Logic Block Size for Random Logic  
D
D
D
D
Q
Q
Q
Q
Logic  
Array  
GLB  
A4  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
A5  
A6  
A7  
— fmax = 125 MHz Maximum Operating Frequency  
— tpd = 7.5 ns Propagation Delay  
Output Routing Pool (ORP)  
Input Bus  
— TTL Compatible Inputs and Outputs  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
0139Bisp/2064  
Fu  
Description  
— 100% Tested at Time of Manufacture  
— Unused Product Term Shutdown Saves Power  
The ispLSI 2064 and 2064A are High Density Program-  
mable Logic Devices. The devices contain 64 Registers,  
64 Universal I/O pins, four Dedicated Input pins, three  
Dedicated Clock Input pins, two dedicated Global OE  
input pins and a Global Routing Pool (GRP). The GRP  
provides complete interconnectivity between all of these  
elements. The 2064 and 2064A feature 5V in-system  
programmability and in-system diagnostic capabilities.  
The ispLSI 2064 and 2064A offer non-volatile  
reprogrammability of the logic, as well as the intercon-  
nect, to provide truly reconfigurable systems.  
• IN-SYSTEM PROGRAMMABLE  
— In-System Programmable (ISP™) 5V Only  
— Increased Manufacturing Yields, Reduced Time-to-  
Market and Improved Product Quality  
— Reprogram Soldered Devices for Faster Prototyping  
• OFFERS THE EASE OF USE AND FAST SYSTEM  
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY  
OF FIELD PROGRAMMABLE GATE ARRAYS  
— Complete Programmable Device Can Combine Glue  
Logic and Structured Designs  
— Enhanced Pin Locking Capability  
— Three Dedicated Clock Input Pins  
— Synchronous and Asynchronous Clocks  
— Programmable Output Slew Rate Control to  
Minimize Switching Noise  
— Flexible Pin Placement  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
The basic unit of logic on these devices is the Generic  
Logic Block (GLB). The GLBs are labeled A0, A1…B7  
(Figure1). Thereareatotalof16GLBsintheispLSI2064  
and 2064A devices. Each GLB is made up of four  
macrocells. Each GLB has 18 inputs, a programmable  
AND/OR/ExclusiveORarray, andfouroutputswhichcan  
be configured to be either combinatorial or registered.  
Inputs to the GLB come from the GRP and dedicated  
inputs. All of the GLB outputs are brought back into the  
GRP so that they can be connected to the inputs of any  
GLB on the device.  
— Lead-Free Package Options  
Copyright©2006LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
August 2006  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
2064_10  
1
1234567...14

中文翻译

下载PDF

与ISPLSI2064A-80LJ84相关器件

型号 品牌 获取价格 描述 数据表
ISPLSI2064A-80LJ84I LATTICE

获取价格

 		EE PLD, 18.5ns, 64-Cell, CMOS, PQCC84, PLASTIC, LCC-84
ISPLSI2064A-80LJN84 LATTICE

获取价格

 		EE PLD, 18.5ns, 64-Cell, CMOS, PQCC84, LEAD FREE, PLASTIC, LCC-84
ISPLSI2064A-80LT100 LATTICE

获取价格

 		EE PLD, 18.5ns, 64-Cell, CMOS, PQFP100, TQFP-100
ISPLSI2064A-80LT100I LATTICE

获取价格

 		EE PLD, 18.5ns, 64-Cell, CMOS, PQFP100, TQFP-100
ISPLSI2064A-80LTN100 LATTICE

获取价格

 		EE PLD, 18.5ns, 64-Cell, CMOS, PQFP100, LEAD FREE, TQFP-100
ISPLSI2064E-100LT ETC

获取价格

 		Electrically-Erasable Complex PLD
ISPLSI2064E-100LT100 LATTICE

获取价格

 		In-System Programmable SuperFAST⑩ High Densit
ISPLSI2064E-135LT ETC

获取价格

 		Electrically-Erasable Complex PLD
ISPLSI2064E-135LT100 LATTICE

获取价格

 		In-System Programmable SuperFAST⑩ High Densit
ISPLSI2064E-200LT ETC

获取价格

 		Electrically-Erasable Complex PLD

与ISPLSI2064A-80LJ84相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证