Datasheet > ISPLSI2032A-80LJ44

ISPLSI2032A-80LJ44

更新时间： 2024-09-15 14:34:07

品牌	Logo	应用领域
莱迪思 - LATTICE		时钟输入元件可编程逻辑
页数	文件大小	规格书
16页	406K
描述
EE PLD, 18.5ns, 32-Cell, CMOS, PQCC44, PLASTIC, LCC-44

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ISPLSI2032A-80LJ44 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	PLASTIC, LCC-44	针数：	44
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.71
其他特性：	YES	最大时钟频率：	57 MHz
系统内可编程：	YES	JESD-30 代码：	S-PQCC-J44
JESD-609代码：	e0	JTAG BST：	NO
长度：	16.5862 mm	湿度敏感等级：	3
专用输入次数：		I/O 线路数量：	32
宏单元数：	32	端子数量：	44
最高工作温度：	70 °C	最低工作温度：
组织：	0 DEDICATED INPUTS, 32 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC44,.7SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	225
电源：	5 V	可编程逻辑类型：	EE PLD
传播延迟：	18.5 ns	认证状态：	Not Qualified
座面最大高度：	4.572 mm	子类别：	Programmable Logic Devices
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	16.5862 mm
Base Number Matches：	1

ISPLSI2032A-80LJ44 数据手册

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Lead-

Package

ispLSI 2032/A

Options

vailable!

In-System Programmable High Density PLD

Features

Functional Block Diagram

• ENHANCEMENTS

— ispLSI 2032A is Fully Form and Function Compatible

to the ispLSI 2032, with Identical Timing

Specifcations and Packaging

— ispLSI 2032A is Built on an Advanced 0.35 Micron

E²CMOS^®Technology

• HIGH DENSITY PROGRAMMABLE LOGIC

Global Routing Pool

(GRP)

— 1000 PLD Gates

— 32 I/O Pins, Two Dedicated Inputs

— 32 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

Logic

Array

GLB

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 180 MHz Maximum Operating Frequency

— tpd = 5.0 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

0139Bisp/2000

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

Description

• IN-SYSTEM PROGRAMMABLE

The ispLSI 2032 and 2032A are High Density Program-

mable Logic Devices. The devices contain 32 Registers,

32 Universal I/O pins, two Dedicated Input Pins, three

Dedicated Clock Input Pins, one dedicated Global OE

input pin and a Global Routing Pool (GRP). The GRP

provides complete interconnectivity between all of these

elements. The ispLSI 2032 and 2032A feature 5V in-

system programmability and in-system diagnostic

capabilities. The ispLSI 2032 and 2032A offer non-

volatile reprogrammability of the logic, as well as the

interconnect to provide truly reconfigurable systems.

— In-System Programmable (ISP™) 5V Only

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

The basic unit of logic on these devices is the Generic

Logic Block (GLB). The GLBs are labeled A0, A1 .. A7

(Figure 1). There are a total of eight GLBs in the ispLSI

2032 and 2032A devices. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/ExclusiveORarray, andfouroutputswhichcan

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

— Lead-Free Package Options

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

August 2006

2032_11

12 3 4 5 6 7...16

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与ISPLSI2032A-80LJ44相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI2032A-80LJI	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI2032A-80LT44	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI2032A-80LT44I	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI2032A-80LT48	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI2032A-80LT48I	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI2032A-80LTN44	LATTICE	获取价格	EE PLD, 18.5ns, 32-Cell, CMOS, PQFP44, LEAD FREE, TQFP-44
ISPLSI2032A-80LTN48	LATTICE	获取价格	EE PLD, 18.5ns, 32-Cell, CMOS, PQFP48, LEAD FREE, TQFP-48
ISPLSI2032A-80LTN48I	LATTICE	获取价格	EE PLD, 18.5ns, 32-Cell, CMOS, PQFP48, LEAD FREE, TQFP-48
ISPLSI2032E	LATTICE	获取价格	In-System Programmable SuperFAST High Density PLD
ISPLSI2032E-110LJ	LATTICE	获取价格	EE PLD, 13ns, CMOS, PQCC44, 0.650 X 0.650 INCH, PLASTIC, LCC-44

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