Datasheet > ISPLSI2032E-200LJ44

ISPLSI2032E-200LJ44

更新时间： 2024-11-05 23:01:19

品牌	Logo	应用领域
莱迪思 - LATTICE		可编程逻辑器件
页数	文件大小	规格书
14页	175K
描述
In-System Programmable SuperFAST High Density PLD

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ISPLSI2032E-200LJ44 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	LCC	包装说明：	PLASTIC, LCC-44
针数：	44	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.78	其他特性：	USE IPLSI2032E-225 FOR NEW DESIGNS
最大时钟频率：	167 MHz	系统内可编程：	YES
JESD-30 代码：	S-PQCC-J44	JESD-609代码：	e0
JTAG BST：	NO	长度：	16.5862 mm
湿度敏感等级：	3	专用输入次数：
I/O 线路数量：	32	宏单元数：	32
端子数量：	44	最高工作温度：	70 °C
最低工作温度：		组织：	0 DEDICATED INPUTS, 32 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC44,.7SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
电源：	5 V	可编程逻辑类型：	EE PLD
传播延迟：	5.5 ns	认证状态：	Not Qualified
座面最大高度：	4.57 mm	子类别：	Programmable Logic Devices
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	16.5862 mm	Base Number Matches：	1

ISPLSI2032E-200LJ44 数据手册

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ispLSI 2032E

In-System Programmable

SuperFAST™ High Density PLD

Features

Functional Block Diagram

• SuperFAST HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

— 1000 PLD Gates

— 32 I/O Pins, Two Dedicated Inputs

— 32 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100% Functionally and JEDEC Upward Compatible

with ispLSI 2032 Devices

Global Routing Pool

(GRP)

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 225 MHz Maximum Operating Frequency

— tpd = 3.5 ns Propagation Delay

Logic

Array

GLB

— TTL Compatible Inputs and Outputs

— 5V Programmable Logic Core

— ispJTAG™ In-System Programmable via IEEE 1149.1

(JTAG) Test Access Port

— User-Selectable 3.3V or 5V I/O (48-Pin Package Only)

Supports Mixed Voltage Systems

0139Bisp/2000

— PCI Compatible Outputs (48-Pin Package Only)

— Open-Drain Output Option

— Electrically Erasable and Reprogrammable

— Non-Volatile

Description

The ispLSI 2032E is a High Density Programmable Logic

Device. The device contains 32 Registers, 32 Universal

I/O pins, two Dedicated Input Pins, three Dedicated

Clock Input Pins, one dedicated Global OE input pin and

a Global Routing Pool (GRP). The GRP provides com-

plete interconnectivity between all of these elements.

The ispLSI 2032E features 5V in-system programmabil-

ity and in-system diagnostic capabilities. The ispLSI

2032E offers non-volatile reprogrammability of the logic,

as well as the interconnect to provide truly reconfigurable

systems.

— Unused Product Term Shutdown Saves Power

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

The basic unit of logic on the ispLSI 2032E device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. A7 (see Figure 1). There are a total of eight GLBs in the

ispLSI 2032E device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/ExclusiveORarray, andfouroutputswhichcan

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

The device also has 32 I/O cells, each of which is directly

connected to an I/O pin. Each I/O cell can be individually

to change without notice.

June 1999

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

2032e_03

12 3 4 5 6 7...14

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与ISPLSI2032E-200LJ44相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI2032E-200LT44	LATTICE	获取价格	In-System Programmable SuperFAST High Density PLD
ISPLSI2032E-200LT48	LATTICE	获取价格	In-System Programmable SuperFAST High Density PLD
ISPLSI2032E-225LJ44	LATTICE	获取价格	In-System Programmable SuperFAST High Density PLD
ISPLSI2032E-225LT44	LATTICE	获取价格	In-System Programmable SuperFAST High Density PLD
ISPLSI2032E-225LT48	LATTICE	获取价格	In-System Programmable SuperFAST High Density PLD
ISPLSI2032LV-60LJ	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI2032LV-60LJI	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI2032LV-60LT44	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI2032LV-60LT44I	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI2032LV-80LJ	ETC	获取价格	Electrically-Erasable Complex PLD

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